CMOD A7-35T Power On Reset and Vivado

[Brumrock]

Hi guys,

I'm VERY new to the CMOD A7-35T and Vivado. Looking at the A7 schematic and hunting around for information on Power On Reset it seems that the Reset line on the FPGA is the Program_b_0 pin (V10). However, I see no signs of the reset button mentioned in the reference manual or any other Power On Reset circuitry except for a 4.7k pull-up. If I try to assign my Reset line to pin V10, Vivado baulks at the suggestion indicating that the pin is reserved.

My question is how is Power On Reset managed on the A7 and is the input assigned in Vivado? I see plenty of examples n Verilog where a reset is used but this always seems to appear out of nowhere, pin out assignments are not present. Perhaps an external PoR is needed?

I have created a PoR scheme using a few flip flops that should work but Vivado provides me with numerous warnings regarding its use as a PoR solution

 I'm using Vivado 2020.2 on Windows 10 and my application is in Verilog.

Thanks for your help.

 

 

 

[JColvin]

Hi @Brumrock,

You are correct that PROGRAM_B would reset the FPGA in its entirety once it is driven Low (as per Table 2-4 in Xilinx's UG470, https://docs.xilinx.com/v/u/en-US/ug470_7Series_Config).

However, as you have noted, the Cmod A7 does not have any on-board way to drive this pin Low; other Digilent boards have a dedicated button wired to this particular FPGA pin, but the Cmod A7 does not. You would have to disconnect power entirely from the Cmod A7 or somehow manually solder an external button to this pin to trigger POR, but I would not recommend attempting the latter.

If you just want to reset your logic, but maintain the bitstream configuration, you can of course always use one of the external pins (or one of the buttons) as your 'reset' pulse.

Let me know if you have any questions.

Thanks,
JColvin