I have an Eclypse Z7 Board with attached ZMOD ADC and DAC boards. I am currently playing around with the Linux Demo-SDK-Projects for the DAC. I have no problem filling the circular output buffer with my desired waveform and grab the periodic signal from the SMA socket.
Unfortunately I struggle with following use-case:
I need to output a single gaussian pulse. To that end I wanted to fill the circular buffer with my desired signal and then only output the pulse once. Once I enable the DAC output, it automatically repeats once it got to the end of the buffer, which is fine for most applications I guess.
With a sample clock of 10 Mhz, and the usual Linux induced latency I am not able to reliably disable the DAC at the end of the circular buffer, since the signal length is 1.66ms at most. I was figuring, that I could probably tweak the FPGA part and add a custom flag that disables the automatic buffer looping but since there are no design sources of the IP blocks available (are there any?) I'm quite a bit lost.
Maybe I missed something, but how can I output the content of the circular buffer only once?
I would be glad, if someone could point me in the right direction.
Question
Jaber29
Hello,
I have an Eclypse Z7 Board with attached ZMOD ADC and DAC boards. I am currently playing around with the Linux Demo-SDK-Projects for the DAC. I have no problem filling the circular output buffer with my desired waveform and grab the periodic signal from the SMA socket.
Unfortunately I struggle with following use-case:
I need to output a single gaussian pulse. To that end I wanted to fill the circular buffer with my desired signal and then only output the pulse once. Once I enable the DAC output, it automatically repeats once it got to the end of the buffer, which is fine for most applications I guess.
With a sample clock of 10 Mhz, and the usual Linux induced latency I am not able to reliably disable the DAC at the end of the circular buffer, since the signal length is 1.66ms at most. I was figuring, that I could probably tweak the FPGA part and add a custom flag that disables the automatic buffer looping but since there are no design sources of the IP blocks available (are there any?) I'm quite a bit lost.
Maybe I missed something, but how can I output the content of the circular buffer only once?
I would be glad, if someone could point me in the right direction.
Best regards
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