How to run the labs of Vivado Desing Suite Tutorial (UG936) on Arty-7 ?

[titijmc]

Hello

I wanted to play with the examples (labs) of the "Vivado Desing Suite Tutorial Programming and Debugging" (UG936) but I only have an Arty-7 board.

In the constraint file and in the pinout information (p.9) I see that the examples use two clock-pins (AD11 for CLK_N and AD12 for CLK_P).

But on my Arty-7 I know only one clock-pin (E3). Is there another one ?

Furthermore is it possible to play these examples on Arty-7 ?

Sorry if you find my question silly but I am a newbie on FPGA and I found no explanation in the Xilinx tutorial.

Thank in advance for any reply

Jack-Michel

 

[zygot]

Trying to follow a tutorial meant to target an FPGA device and board that isn't the one that you want to work with can be a problem for those just getting started with FPGA development. In the case of UG936 the pin locations are for the KC705 board. Normally, I'd mention that you can use the tools to build a design that targets most devices and boards. You just can't use the bitstream file to configure hardware that doesn't use the exact device ( and package ) or a different board. The free tools don't support all devices, notably Virtex and Kintex; and the KC705 uses a Kintex device. So, you can go through all of the steps of creating a bitstream, except the final step... which actually creates the bitstream file, unless you have a special device license. This isn't necessarily a show stopper.

Reading through the Xilinx tutorials is good.. with limitations. You can learn how the tools work and how the preferred Xilinx IPI design flow works.

Having said all of that you need to know if your board is an Arty A7 or Arty S7, as one uses an Artix device and the other a Spartan 7 device. Also, I believe that there are different versions of the boards that use FPGA devices with different packages; that is, different versions of the Arty board will have different pin locations.

So, keep reading the Xilinx documentation. But when you want to see a design working on your board you will have to use the proper constraints for your board. This is important because you don't want to create a design that ties a pin to an output buffer if the hardware connects it to a external device that is driving the pin.

Whether you want to use the master constraints file for your board or the board files depends on your design flow. For an HDL design flow you will likely use a modified version of the Digilent supplied master constraints file. For an IPI design flow you will probably want to use the Digilent supplied board files. In the former case you will be responsible for making sure that the constraints are correct. In the later case Vivado will control this. The truth is that either one is possible for either flow. The problem is that there is a lot of learning to do for someone just getting started and simpler is easier. Things can get pretty confusing very quickly, and Xilinx documentation is frequently confusing even for expert FPGA developers.

Personally, I think that using the HDL flow is better for beginners.. as long as there is some guidance available. Unfortunately, finding good all HDL demos that users can build for a particular board are hard to come by. FPGA vendors and FPGA board vendors prefer the IPI design flow because it's less complicated and expensive for them as they can control use cases. Edited April 18, 2022 by zygot

[titijmc]

Thank you @zygot for your long answer but I was aware of most of things that you put in it.

My question was essentially about the clocks : since the lab 1 example of UG936 uses two clock-pins (AD11 for CLK_N and AD12 for CLK_P) and I know only one clock-pin on my Arty-A7 (E3), I wonder if it is possible to run this example on my board and which are the pin I have to use instead of AD11 and 1D12.

Regards

[zygot]

Generally, there is no requirement for using a differential external clock for all but the most critical designs. So, I suspect that yes... provided that you alter the source code, you can port a version of the KC705 UG936 design example to your board.. considering the limited IO of the design and the fact that it is mostly VHDL sources.

As I recall, the KC705 external differential clock is 200 MHz and the Arty single ended external clock modules are lower frequency. I don't have the sources available to look through.

Do get the Digilent master constraints file for your board as well as the schematic so that you can work out which pins to connect your toplevel entity to. I'd be surprised if the design didn't have an MMCM or PLL in it. If so that you mean some changes to instantiating that resource. The Kintex on the KC705 is a much more capable FPGA device so what runs at 200 MHz on that platform might have timing closure issues for your board. There might also be a shortage of other resources; it's hard to tell without looking at the source code.

But there's no harm in trying. So, go for it. Just to be clear... you will have to use the schematic for your board to select the proper pin location constraints for any port to your board. All of the pin locations will have to be changed. Alternately, you could use the Digilent reference manual for your board but I'd advise against that because schematics are almost always correct and other documentation, even master constraints files, sometimes have errors. The only FPGA board that I've ever run into with an incorrect schematic is the FPGA-Net-CML-1G, which has a faulty symbol for the QDRII+ memory device.

You should read the Series 7 SelectIO and Clocking resources reference guides before embarking on a design; even a port of a demo meant for a different board and device family.

Last note: Make sure that the signal names on the toplevel port match EXACTLY the signal names on your constraints. If you manage to get through bitgen, check the pin assignments against the schematic to make sure that they are correct. Edited April 18, 2022 by zygot