ZyboZ7 csi

[mdale_photonicscience]

I have a few questions. Is there any thoughts on updating the demo apps for csi camera interface to the latest version so as to support v2 raw16bit and 1.5gbit speed and 4 lanes as the latest I can find is 2019.1 which is still pre-production?

how do I add a physical pin to the current design? Basically I want to add the axi spi and then add a port but the port appears as a bd_spi_clk etc but does not show up as a port in the io pin selection and cannot add it via talc because I can only find it via get_bd_ports not get_ports? 

[elodg]

Our demo apps and IP support our own camera offering, which is limited to the Pcam 5C for now. There are no immediate plans to introduce new features to our CSI-2 IP. Xilinx's CSI-2 offering has become free in the mean time, which might be the solution for you.

I don't fully understand your second query, you can always use Vivado Block Design to make the necessary changes.