Problems with Xilinx MIG on Arty S7

[Dacobi]

Hi

I very new to FPGAs and I'm trying to get MIG to work on the Arty S7

I created a native MIG by modifying these files https://github.com/Digilent/digilent-mig

And then used this example as a base: https://numato.com/kb/simple-ddr3-interfacing-on-skoll-using-xilinx-mig-7/

I can create a bitsteam without errors, but it doesn't work. Calibration never succeeds.

I do get one critical error. This line fails with "no such object"

set_property LOC MMCME2_ADV_X1Y0 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i }]

 

I've created a clk_wiz to output 200mhz from the base clock of 100mhz and set clk_ref_i to 200mhz and sys_clk_i to 100mhz.

 

Any help would be really appreciated! 

   

[Dacobi]

I think I got it working.

LEDs for passed calibration and read/write test now lights up.

The problem was in my clock divider. somehow I ended up with a clock much higher than 200mhz.