I am doing the implementation of a design in vivado at 25MHz frequency in Arty A7 100T fpga board, while doing that i am getting a critical warning that 2883 nets are not routed due to routing congestion even though i am setting the pblock utilization at 50% during floorplanning and the congestion report is not showing where the congestion is. So i am stuck with this design at implementation stage, can you guys suggest how to resolve this congestion.
I am attaching the screenshot of the congestion report and the critical warning that came in the implementation log file.
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Vybhav MN
I am doing the implementation of a design in vivado at 25MHz frequency in Arty A7 100T fpga board, while doing that i am getting a critical warning that 2883 nets are not routed due to routing congestion even though i am setting the pblock utilization at 50% during floorplanning and the congestion report is not showing where the congestion is. So i am stuck with this design at implementation stage, can you guys suggest how to resolve this congestion.
I am attaching the screenshot of the congestion report and the critical warning that came in the implementation log file.
Thanks
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