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How to resolve this routing congestion in my design that is occurring during implementation in ARTY A7 100T?


Vybhav MN

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I am doing the implementation of a design in vivado at 25MHz frequency in Arty A7 100T fpga board, while doing that i am getting a critical warning that 2883 nets are not routed due to routing congestion even though i am setting the pblock utilization at 50% during floorplanning and the congestion report is not showing where the congestion is. So i am stuck with this design at implementation stage, can you guys suggest how to resolve this congestion.

 

I am attaching the screenshot of the congestion report and the critical warning that came in the implementation log file.

 

Thanks

Congestion_report.png

Implemenation_Log.png

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Your design, as far as the synthesis tool understands it, seems to be running out of resources.

It's hard to make a conjecture about what the problem is without more information about the design. But, there are certainly things that you could try. You could try implementing a smaller version of the design. You could try restructuring the design. In the case of a flaw in your source, you could comb through the synthesis messages for clues as to what's causing the issue.

What happens when you try an run your RTL testbench simulation? Is there any device target that works in simulation?
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7 hours ago, zygot said:

Your design, as far as the synthesis tool understands it, seems to be running out of resources.

It's hard to make a conjecture about what the problem is without more information about the design. But, there are certainly things that you could try. You could try implementing a smaller version of the design. You could try restructuring the design. In the case of a flaw in your source, you could comb through the synthesis messages for clues as to what's causing the issue.

What happens when you try an run your RTL testbench simulation? Is there any device target that works in simulation?

Hey i got the mistake that was in the constraint file. The create clock command itself was not executing hence the was not created and all those timing and routing violations happened due to that. In the log this was just an info not even warning or an error so i didn't noticed that mistake and yeah i removed all those unnecessary constraints and kept just the create clock and pins one.

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