Programming the flash from Vitis on a Genesys-ZU

[John J]

I get the error listed below in Vitis 2021.2 when I use the Program Flash option and have tried several "Flash Type" settings in the programming window.

• Is there a procedure for getting this to work?
• Are there any special steps when booting from flash that need to be taken to create a proper boot image?

Thank you for your help.

Quote

jedec_spi_nor flash@0: unrecognized JEDEC id bytes: 8c, 20, 08
Failed to initialize SPI flash at 0:0 (error -2)
ZynqMP> ERROR: [Xicom 50-186] Error while detecting SPI flash device - unrecognized JEDEC id bytes: 8c, 20, 08
Problem in running uboot
Flash programming initialization failed.

ERROR: Flash Operation Failed

 

[elodg]

Hi,

This is very odd because the onboard flash is an ISSI IS25LP256D (manual), with JEDEC ID 9d, 60, 19 (datasheet).

Both Vitis and Vivado flash programming requires an FSBL to correctly configure clocking and pinout for the QSPI controller. I suggest you look at the hardware configuration (Vivado), and the hardware platform and fsbl in Vitis.

Second, our Software Support is for 2020.1, where I could program the flash successfully:

$ git clone --recurse-submodules https://github.com/Digilent/Genesys-ZU.git
$ git checkout --recurse-submodules 3EG/HELLO-WORLD/2020.1-1
$ git submodule update --recursive --init

Open Vitis workspace Genesys-ZU/sw/ws

xsct% source [getws]/../src/checkout.tcl

Set FSBL path in hardware platform project to Genesys-ZU/sw/ws/3eg_fsbl/Release/3eg_fsbl.elf

Re-build 3eg_master system project to get the hello-world boot.bin.

Xilinx -> Program Flash

****** Xilinx Program Flash
****** Program Flash v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.


WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-Genesys ZU - 3EG-210383AF7ECEA
	Device 0: jsn-Genesys ZU - 3EG-210383AF7ECEA-14710093-0
	Device 1: jsn-Genesys ZU - 3EG-210383AF7ECEA-5ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
Using default mini u-boot image file - C:/Xilinx/Vitis/2020.1/data\xicom\cfgmem\uboot\zynqmp_qspi_x4_single.bin
===== mrd->addr=0xFF5E0204, data=0x00000EEE =====
BOOT_MODE REG = 0x0EEE
WARNING: [Xicom 50-100] The current boot mode is SD1-LS.
If flash programming fails, configure device for JTAG boot mode and try again.
Downloading FSBL...
Running FSBL...
Finished running FSBL.




U-Boot 2020.01-08125-g1c9cef3 (May 05 2020 - 15:11:32 -0600)



Model: ZynqMP MINI QSPI SINGLE

Board: Xilinx ZynqMP

DRAM:  WARNING: Initializing TCM overwrites TCM content

256 KiB

EL Level:	EL3

Multiboot:	0

In:    dcc

Out:   dcc

Err:   dcc

ZynqMP> sf probe 0 0 0


SF: Detected is25lp256 with page size 256 Bytes, erase size 64 KiB, total 32 MiB

You can also follow the instructions here to get the hello world project without git: https://digilent.com/reference/programmable-logic/genesys-zu/demos/hello-world

Edited March 25, 2022 by elodg

[John J]

The U-Boot that Vitis 2021.2 uses does not work with the Genesys board.  The "sf probe" fails.

Using default mini u-boot image file - /tools/Xilinx/Vitis/2021.2/data/xicom/cfgmem/uboot/zynqmp_qspi_x4_single.bin
U-Boot 2021.01-00102-g43adebe (Oct 11 2021 - 01:44:06 -0600)
 

[John J]

The U-Boot that Vitis 2021.2 provides does not recognize the flash on the Genesys board.  The "sf probe" fails. 

It looks like the Digilent FSBL is loading properly, but I don't think the PL is getting programmed correctly.  The "Done" LED is not lit up after the process fails, and there is no clock on the QSPI showing on my scope.

Is there a way to tell of the PL is getting programmed with the correct bitstream?

Terminal output during programming

Xilinx Zynq MP First Stage Boot Loader
Release 2020.1   Mar 23 2022  -  17:53:51
Reset Mode      :       System Reset
Platform: Silicon (4.0), Running on A53-0 (64-bit) Processor, Device Name: XCZU3EG
Digilent Genesys ZU board-specific init
In JTAG Boot Mode
PMU-FW is not running, certain applications may not be supported.
Protection configuration applied
Exit from FSBL

Output from either the Console window when using the Vitis GUI and from the XSCT console when typing the commands.

.
Using default mini u-boot image file - /tools/Xilinx/Vitis/2021.2/data/xicom/cfgmem/uboot/zynqmp_qspi_x4_single.bin
===== mrd->addr=0xFF5E0204, data=0x00000000 =====
BOOT_MODE REG = 0x0000
Downloading FSBL...
Running FSBL...
===== mrd->addr=0xFFD80044, data=0x00000000 =====
===== mrd->addr=0xFFD80044, data=0x00000000 =====
===== mrd->addr=0xFFD80044, data=0x00000000 =====
===== mrd->addr=0xFFD80044, data=0x00000003 =====
Finished running FSBL.
...
U-Boot 2021.01-00102-g43adebe (Oct 11 2021 - 01:44:06 -0600)
...
ZynqMP> sf probe 0 0 0
jedec_spi_nor flash@0: unrecognized JEDEC id bytes: 8c, 20, 08
...

Using the OOB PetaLinux U-Boot, I get the following.

ZynqMP> sf probe 0 0 0
SF: Detected is25lp256 with page size 256 Bytes, erase size 64 KiB, total 32 MiB

I'm just wondering if anyone has ideas on pinning this down a little closer, it will be kind of painful to go back to using the older Vitis at this point.

Thanks.

Edited April 7, 2022 by John J

[elodg]

Using Vivado Hardware Manager 2021.2 everything seems to be working:

connect_hw_server: Time (s): cpu = 00:00:02 ; elapsed = 00:00:21 . Memory (MB): peak = 1414.113 ; gain = 0.000
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210383AFDD5CA
open_hw_target: Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 3092.043 ; gain = 1677.930
current_hw_device [get_hw_devices xczu5_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xczu5_0] 0]
INFO: [Labtools 27-1435] Device xczu5 (JTAG device index = 0) is not programmed (DONE status = 0).
current_hw_device [get_hw_devices arm_dap_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices arm_dap_1] 0]
current_hw_device [get_hw_devices xczu5_0]
create_hw_cfgmem -hw_device [lindex [get_hw_devices xczu5_0] 0] [lindex [get_cfgmem_parts {is25lp256d-qspi-x4-single}] 0]
set_property PROGRAM.BLANK_CHECK  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.ERASE  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.CFG_PROGRAM  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.VERIFY  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.CHECKSUM  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
refresh_hw_device [lindex [get_hw_devices xczu5_0] 0]
INFO: [Labtools 27-1435] Device xczu5 (JTAG device index = 0) is not programmed (DONE status = 0).
set_property PROGRAM.ADDRESS_RANGE  {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.FILES [list "C:/git/Zyboz7_rtl8211f/ws/hello_world_system/_ide/bootimage/BOOT.bin" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.BIN_OFFSET {0} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.ZYNQ_FSBL {C:/git/zuca_bm_bist/ws/5ev_fsbl/Release/5ev_fsbl.elf} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.BLANK_CHECK  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.ERASE  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.CFG_PROGRAM  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.VERIFY  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
set_property PROGRAM.CHECKSUM  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
startgroup 
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu5_0] 0]]
f probe 0 0 0
Performing Erase Operation...
Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 1 sec.
Performing Program Operation...
Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 1 sec.
Performing Verify Operation...
INFO: [Xicom 50-44] Elapsed time = 2 sec.
Verify Operation successful.
INFO: [Labtoolstcl 44-377] Flash programming completed successfully
program_hw_cfgmem: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 3173.844 ; gain = 0.000
endgroup

In Vitis 2021.2 to avoid creating a hardware platform and project the GUI seems to require for flash programming I used XSCT instead. It works there too:

xsct% exec program_flash -f 5ev_fsbl.elf -fsbl 5ev_fsbl.elf -verify -flash_type qspi-x4-single

****** Xilinx Program Flash
****** Program Flash v2021.2 (64-bit)
  **** SW Build 1967 on 2021-10-14-04:42:58
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ TCP:localhost:3121

Retrieving Flash info...

Initialization done
Using default mini u-boot image file - d:/Xilinx/Vitis/2021.2/data\xicom\cfgmem\uboot\zynqmp_qspi_x4_single.bin
===== mrd->addr=0xFF5E0204, data=0x00000000 =====
BOOT_MODE REG = 0x0000
Downloading FSBL...
Running FSBL...
===== mrd->addr=0xFFD80044, data=0x00000000 =====
===== mrd->addr=0xFFD80044, data=0x00000003 =====
Finished running FSBL.




U-Boot 2021.01-00102-g43adebe (Oct 11 2021 - 01:44:06 -0600)



Model: ZynqMP MINI QSPI SINGLE

Board: Xilinx ZynqMP

DRAM:  WARNING: Initializing TCM overwrites TCM content

256 KiB

EL Level:	EL3

Multiboot:	0

In:    dcc

Out:   dcc

Err:   dcc

ZynqMP> sf probe 0 0 0


SF: Detected is25lp256 with page size 256 Bytes, erase size 64 KiB, total 32 MiB

ZynqMP> Sector size = 65536.
f probe 0 0 0


Performing Erase Operation...
sf erase 0 90000


SF: 589824 bytes @ 0x0 Erased: OK

ZynqMP> Erase Operation successful.
...
ZynqMP> Program Operation successful.
...
ZynqMP> INFO: [Xicom 50-44] Elapsed time = 6 sec.
Verify Operation successful.

Flash Operation Successful

While the USB-UART terminal has the FSBL messages:

Xilinx Zynq MP First Stage Boot Loader
Release 2020.1   Apr 16 2021  -  16:22:31
Reset Mode      :       System Reset
Platform: Silicon (4.0), Running on A53-0 (64-bit) Processor, Device Name: XCZU5EV
Digilent Genesys ZU board-specific init
In JTAG Boot Mode
PMU-FW is not running, certain applications may not be supported.
Protection configuration applied
Exit from FSBL
Xilinx Zynq MP First Stage Boot Loader
Release 2020.1   Apr 16 2021  -  16:22:31
Reset Mode      :       System Reset
Platform: Silicon (4.0), Running on A53-0 (64-bit) Processor, Device Name: XCZU5EV
Digilent Genesys ZU board-specific init
In JTAG Boot Mode
PMU-FW is not running, certain applications may not be supported.
Protection configuration applied
Exit from FSBL
Xilinx Zynq MP First Stage Boot Loader
Release 2020.1   Apr 16 2021  -  16:22:31
Reset Mode      :       System Reset
Platform: Silicon (4.0), Running on A53-0 (64-bit) Processor, Device Name: XCZU5EV
Digilent Genesys ZU board-specific init
In JTAG Boot Mode
PMU-FW is not running, certain applications may not be supported.
Protection configuration applied
Exit from FSBL

Could you try the same with the attached FSBL for 3EG? Are you on JTAG mode?

3eg_fsbl.elf

Edited April 8, 2022 by elodg

[John J]

Hi @elodg

After fixing one broken include path in my existing project, other include paths have been corrupted by Vitis.  I'm just going to have to recreate the Vitis project again and add my existing code and HW design.  I've been suspecting that the flash programming issue is in the project, so I already wanted to recreate it.

I'd like to use your method of starting with the repos, but when I have used that method in the past, I run into an issue.

After running the checkout script, I get a "Workspace already exists and needs to be closed first" error.

I am obviously missing something simple here, but I have not found a solution to the problem, which is why I've just been importing the zip file.

I would like to get the method you described above working.

Do you have any suggestions.

Thank you,

John J

[elodg]

You are hijacking this thread with other issues, which will confuse others in need of help and us as we are debugging this. Our Git workflow is described here: https://digilent.com/reference/programmable-logic/documents/git?redirect=1#vitis_sw_workspaces.  The error message should have a preceding line which tells you exactly what to do:

Quote

WARNING: workspace is not empty. Close Vitis or XSCT to relinquish control and run the cleanup scripts. Re-run checkout.tcl afterwards.

If you are still having issues with the Git workflow, please start a different thread.

-----------------

Getting back to the flash issue at hand. The FSBL I attached, your Vivado/Vitis installation, and the commands listed in the post are the only things needed to confirm whether you are having a hardware or a software issue. It is essential that we eliminate an improbable faulty board first.

[elodg]

@John J,

Have you managed to figure out what the issue was with programming the flash?

[John J]

@elodg

I was not able to get 2021.2 to program the flash.  The boot loader returns an incorrect flash ID.  As I mentioned above, the U-Boot included for programming the flash returns the same bad ID.  I don't understand why it works differently for me.  I'd like to try 2022.1 to see how it behaves, but creating a new project becomes more complicated, due to the lack of the older library versions.

Vitis 2020.1 will program the flash, but I've found that in 2020.1 the Genesys ZU "Hello World" project gets corrupted very easily and in multiple ways.  When changing anything in the project structure, I often find that the build breaks for reasons that appear to not be related to the actual change.  Tracking down the cryptic Vitis errors is a real struggle.

I would like to be able to create a "clean" project, but have not successfully pulled in the Digilent FSBL into a new project.  What would be very helpful is a more detailed guide on importing the custom Digilent FSBL into a new project.

Thank you for your help.

[elodg]

Hey @John J,

Could you tell me where is the FSBL you are using with "Program Flash" is coming from? I noticed you are using Vitis 2021.2, but the FSBL is 2020.1.

[John J]

Hi @elogd,

At that time, I was using the FSBL included in the 5EV Hello World Project that was current at the time.  I was not able to determine if Vitis was using the correct FSBL or one of it's own.

I have not investigated this further and have switched to using 2022.1 and testing 2022.2 with the Digilent 5EV FSBL that was updated in August.  It may no longer be an issue, as I think I was able to program using 2022.1.  I'm not positive about that.

JJJ

[elodg]

There is a possible bug in the Vivado/Vitis 2021.1-2022.1 mini u-boot image used to program the flash. The mini u-boot image does not set a valid clock frequency, clock delay and data delay in certain cases. A workaround for the Genesys ZU is to use a hardware platform with a QSPI reference clock <= 250 MHz, which should make the flash programming work again. Taking a 2020.1 mini u-boot image and overwriting the one in later versions also works. This has been reported to Xilinx, let's see what fix they come up with.

[John J]

Thanks @elodg.

I will have to try this under 2022.1 and 2022.2, as I have not tried either yet.

I appreciate the update.

[Ankit Patel]

https://blog.csdn.net/m0_52850847/article/details/137159548

 

I also had the same problem with my Arty Z7 20 board. I found the solution as mentioned in above link. I need to change parameters of my Zynq PS system and I can now flash my boot image into on board flash memory.