High Speed Pulses in Nexys A7 Board

[kannan.sasikumar]

For my project I have high speed pulses coming from an APD that is to processed by the FPGA, but the Nexys A7 board  does not have any obvious pins to accept the fast pulses, since there are no pins with the impedance matching.

So is there a way around this issue, are there any pins I can use with my pulses getting attenuated completely or will i have to use an external board just for the impedance matching before i send the pulses into the Dev board??

Thanks and Regards

Kannan

[zygot]

What's an APD?

Can you be more specific about the external logic type coming into your FPGA board; such as minimum pulse width, repetition rate, logic family, etc.

[kannan.sasikumar]

Hi @zygot

APD is an Avalanche Photo Diode, we are implementing a particle size analyzer and for that the liquid is illuminated by a laser and then when ever light hits a particle it is reflected and then APD captures it and sends out a pulse of 8ns high and then 20ns deadtime. Pulse will repeat in a non uniform fashion since pulses are generated only when a particle hits the light from the source.

So i need to know if the pulse can be send to the FPGA so that a counter can count the pulses.

I did not understand what u meant by logic family is it in relation to the FPGA or the APD?

Thanks and Regards

Kannan

[zygot]

Oh, that APD

FPGA devices have pins connected to IO banks that can be powered by a range of voltages. Depending on the bank Vccio voltage you can use pins tied to these IO banks with a selection of various logic families found in devices that you might want your FPGA to interact with. The guide for Xilinx Series 7 FPGA IO pin logic is ug471.

An Avalanche Photo Diode is not a member of a logic family. There are a lot of traditional logic families and sub-variants that were developed over the years. Logic that drives signals have characteristics like output impedance (current drive capability) and a few more specifications. For single-ended logic that drives a signal, certain additional characteristics are important; like slew rate, guaranteed max/min output voltage indicating a logic 1, guaranteed max/min output voltage indicating a logic 0, etc. For single-ended logic that receives signals there are mirror characteristics to be considered. For receivers the min/max voltages for logic 1 and logic 0 are extremely important. Typical programmable logic can be used with a few but not all traditional logic families depending on the voltages supplies to the IO banks. Ideally, when connecting logic drivers to logic receivers ( FPGA devices or whatever ) you want to match receiver impedance to the driver impedance, and usually connect them via wires that have the same effective impedance. This part of logic design can get pretty complicated. Some single ended logic families require specific termination schemes. All may require some type of termination scheme depending on the slew rate and toggle rate that the signal exhibits. As you probably know, impedance involves more than just resistance and is frequency dependent. One can view the connections between logic driver and logic receiver as a transmission line with a bandwidth range dependent on driver slew rate. This view might be important for pulsed signals. Understand that slew rate for logic signals going from 0 --> 1 are not always the same as for signals going from 1 --> 0. It may not be obvious, but most traditional single-ended logic receivers have voltage regions that are not defined as either a logic 1 or a logic 0. You can read the datasheet for a traditional logic device for the details. Connecting drivers to receivers is a topic of study in its own right.

Given that a diode lacks a driver exhibiting controlled characteristics designating binary values as described above you should expect that a bit of logic interface design is necessary to connect it to a traditional logic device, including an FPGA. Even traditional logic families have characteristics that are only guaranteed over certain temperature spans and logic power supply spans. This is an additional complication for what you want to account for if you want consistent results.

So, what you need is a logic design that turns the output of your APD into something that is compatible with one of the available IOSTANDARD for a given pin on your board.

Edited March 9, 2022 by zygot

[kannan.sasikumar]

Could u pls elaborate on what kind of logic design i should be implementing, should i design an impedance network for impedance matching??

Also can i use the pmod pins in the dev board to directly feed the apd out to the fpga, will the attenuation be so high that pulse will be heavily clobbered and hence undetectable?

 

[zygot]

You need the schematics for your board and a read through of ug471; this will allow you to select an IOSTANDARD and possibly a termination scheme. Vendors of photo diodes usually provide application notes for such components. If you have a packaged APD product then you need technical information from that vendor.

Impedance matching is just one aspect of a workable design. Digilent standard PMOD pins have a 200 ohm series protection resistors and likely not an optimal trace routing that complicates such a design and limits bandwidth. The so-called differential high-speed PMOD pins have no series resistors and possibly improved trace routing. The there is the matter of what's between your ADP and the PMOD pin in terms of wiring and power supply. Your choices are likely between finding a suitable 3.3V CMOS or TTL per-fabricated product or developing some expertise in logic/analog design. In theory it should help if you are an EE but such formal preparation is by no means a requirement. Either way, you need to have a good understanding of how your sensor interface works to achieve robust results.

[kannan.sasikumar]

So should i try  by using the pmod pins and if it doesnt i ll try the logic required between APD and pmod??

Also could u please elaborate a bit on the 3.3V CMOS/TTL???

Thanks and Regards

Kannan

 

[zygot]

There's no harm in experimentation... well at least not if it's knowledge based and takes all relevant parameters into consideration. ( and knowing what that means involves a bit of knowledge ) The first step is to read the relevant material for all components involved. Start with ug471.

In general FPGA inputs are a bit safer and easier than outputs, as long as the FPGA pin isn't exposed to excessive voltage levels. One way to expose your FPGA pin ( input or output ) to excessive voltage levels is through ESD.

FPGA devices, and in particular FPGA development boards, aren't necessarily the ideal route to someone not particularly interested in embarking on a self-directed educational journey in order to complete a project. There are PSoC devices and boards as well as traditional uControllers that might make more sense. I'd be surprised if you couldn't find that something along the lines of what you want to do exists in the RPi or Arduino ecosystems. Your project, in particular, is probably not one well suited to a programmable logic solution; unless you are an expert in FPGA design and just want to try out an new challenge that is a bit more expansive than basic FPGA development. I'm getting the sense that you are more interested in doing a software project than a hardware project.

Understand that Digilent FPGA development boards, for the most part and like most low cost FPGA development board vendors, are designed to be used within a limited and controlled add-on board ecosystem; in Digilent's case this is PMOD related boards. Unfortunately, Digilent's support of their ecosystem isn't consistent for everything in it. So, as a customer I'd first want to know if their products and support provides a solution to my project. Customers with advanced skills can often, but not always, figure out a way to use an FPGA development board to accomplish what an ecosystem doesn't. My assumption is that someone with those advanced skills knows how ascertain what the required questions to creating a custom solution are and are generally able to find answers for themselves. Not having the pertinent advanced skills is only a problem if you don't have the time or interest in acquiring them.

Edited March 10, 2022 by zygot

[kannan.sasikumar]

Hi @zygot

Thank you for ur suggestions i ll try with the pmod and see what happens and then move to other options as and if necessary

the FPGA was the clients requirement since  their previous board uses them and there are few other functionalities being implemented which have time constraints

Thanks and Regards

Kannan

 

[kannan.sasikumar]

@ocanturan26 which demo r u referring to??

 

[kannan.sasikumar]

@zygot i monitored the pulse from the APD it has 4V plus and the around 1V negtv amplitudes so is there any pin in the board to which i can give this directly oru should i use a level shifter ??

[zygot]

As I tried to explain earlier, what you want to do is going to involve some design expertise that is more complicated than a simple logic or level shifter approach. I don't think that the purpose of this forum is to provide such design services [for free] or serve as a broker between client and designer.

[kannan.sasikumar]

@zygotthank u and sorry if my questions were a bit too much...