ozgur Posted February 23, 2022 Share Posted February 23, 2022 Hello all I want to run the sobel filter which is published in the digilent project forum :https://projects.digilentinc.com/adam-taylor/fpga-based-edge-detection-using-hls-192ad2?f=1 But when i open the project with Vivado 2019.1, it ask to update the IPs. I do it but then i am getting error for design_1_image_filter_0_1.xci. It is locked. I am new in this field and i do not know how to solve this. Thanks for helps in advance. Link to comment Share on other sites More sharing options...
0 elodg Posted March 25, 2022 Share Posted March 25, 2022 The project seems to have been written in 2017.4 (https://github.com/ATaylorCEngFIET/Hackster/blob/430230fc0cfca0c2108baed7470be8551cf9165c/Sobel_zybo_z7/block_compile.srcs/sources_1/bd/design_1/design_1.bd#L2). If you are a beginner, it is best to use the same Xilinx tool version. Link to comment Share on other sites More sharing options...
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ozgur
Hello all
I want to run the sobel filter which is published in the digilent project forum :https://projects.digilentinc.com/adam-taylor/fpga-based-edge-detection-using-hls-192ad2?f=1
But when i open the project with Vivado 2019.1, it ask to update the IPs. I do it but then i am getting error for design_1_image_filter_0_1.xci.
It is locked. I am new in this field and i do not know how to solve this.
Thanks for helps in advance.
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