getting DDR working from RTL on Zybo/Zynq

[okonomiyonda]

I'm new to Zynq and trying to get DDR3 working on my Zybo Z7-20, and I'm having some issues. When trying to do reads, I do think m_axi_arready is high indicating the slave can take requests, but I never get any responses back on the read data channel. If I validate the design, I get two weird messages. First is a warning about two unconnected address segments, and the other says that interface pin m_axi is not connected to any clock pin, which is weird because I don't have anything in my RTL file called m_axi

General setup: I am created the Zynq in block design view, ran configure to set it up for the Zybo, and enabled high performance slave HP0. I then take my top level RTL module, which contains a test for the simple AXI master I wrote, and import it into the block design view. Finally, I hook up the AXI ports of my RTL module to HP0, and hook up the clock to the sysclk defined in the constraints file. See attached file for reference.

Assumptions:

0) I don't need MIG. AFAICT, MIG is only needed when you need to generate soft DDR controller IP, and not when you have a hard controller like in the Zynq

1) the "correct" way the use the PL and PS together is to instantiate the Zynq in the block design, and then add an instance of my top level RTL module to the design. I saw some people do the opposite, and instantiate the Zynq in their top level RTL module, but I didn't look into how to connect some of the many ports I didn't recognise

2) I can have my RTL module take in the external sysclk, and also output it as the AXI clock S_AXI_HP0_ACLK

3) I can directly hook up my AXI master to HP0 without needing any fancy other things inbetween. See attached image

4) I assume the PL view of the memory space wants to match the address map in ug585-Zynq-7000-TRM.pdf. That is to say DDR seems to go from 0x0008_0000 ~ 0x3FFF_FFFF. The test read address I am using is 0x0010_0000. I see there is an address editor and address map in Vivado, but I've not yet worked out if I need to mess with that for this test

5) I don't need to (at first) mess with S_AXI_HP0_FIFO_CTRL. But it might be useful for simplifying my master later on

6) I assume AXI3 (memory mapped) is what I want for this board

So that's about it. It could very well be a stupid bug in my AXI master, but I wanted to check to make sure the above assumptions were valid.  It could also be my inability to use Vitis. And since I am new to Zynq, I'm not yet sure how to simulate anything in Vivado when the PS is involved, especially DDR stuff. I am also not sure how HW debug works in Vitis, or if there is some way to debug hardware like normal in Vivado.

I apologise if this is a silly question, but either my googling skills have atrophied, or there really isn't a single example/tutorial on how to use Zynq DDR from RTL on the whole internet. So yeah, I probably am just failing at searching, but everything seems to involve only the PS side, or if it did involve PL, it was only AXI IP and no RTL. 

Edited February 21, 2022 by okonomiyonda
forgot one question

[elodg]

I admire your courage to write an RTL module with a master AXI4-Full interface. The validation errors stem from not having the m_axi interface connected (maybe only partially defined), but rather its composing signals individually.

I think for proper AXI4 interface definition that you can use in block design you need to create a custom IP, that has all the AXI magic defined.

Also pay attention to reset. The Zynq needs to be configured and out of reset before the S_AXI_HP0 port can respond.