arty z7-20 PMOD RGB OLED in vivado 2021.1 using ip core PMODOLEDrgb_v1.0 critical warning

[Rai Taimoor Ali]

I am trying to implement rgb oled using ip core provided by digilent in arty z7-20 using JA pmod connector.

critical warnings(31):

• [IP_Flow 19-4965] IP PmodOLEDrgb_axi_quad_spi_0_0 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'digilentinc.com:arty-z7-20:part0:1.0'. Please update the project settings to match the packaged IP.
• [IP_Flow 19-4965] IP PmodOLEDrgb_axi_gpio_0_1 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'digilentinc.com:arty-z7-20:part0:1.0'. Please update the project settings to match the packaged IP.
• [IP_Flow 19-4965] IP PmodOLEDrgb_pmod_bridge_0_0 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'digilentinc.com:arty-z7-20:part0:1.0'. Please update the project settings to match the packaged IP.
• [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
• [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values.

 

[JColvin]

Hi @Rai Taimoor Ali,

The critical warnings about how the Pmod IP was originally created with a different board selected can safely be ignored.

As for the negative DQS skew values, this is due to a change in design recommendations by Xilinx; you can read more about it in the Hardware Errata here: https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual#hardware_errata.

Let me know if you have any questions.

Thanks,
JColvin

[Rai Taimoor Ali]

@JColvin thanks you sir. link helped a lot.