Propagation delay differences? - Cmods: S6, A7-15T, A7-35T

[rehsd]

For a simple circuit such as that in the image below, will I see a difference in propagation delays (at each gate) when implemented on the three different Cmods (S6, A7-15T, A7-35T)? I am working to understand general timings of these Cmods. I have an A7-35T and will implement the circuit and review timings. I'm curious if a less expensive S6 will have similar timings or if it will be slower. Related, I'm looking to understand how these timings compare to discrete ICs in the 74AC series. Will an FPGA be faster or slower than the comparable logic ICs (74AC series)? Thanks!

 

Edit: I implemented the following design on the Cmod S7, A7-15T, and A7-35T. I did not test the S6, as it's not supported in Vivado. From what I am seeing, it seems like the two A7 Cmods have identical delays, and the S7 is a bit slower. I would assume then that the S6 would be slower than the S7.

As I look at Total Delay, the values seem lower than the total delay would be with discrete ICs. Based on this, my interpretation is that this logic in these Cmods would be faster than an equivalent circuit with discrete ICs. Does that sound right?

 

 

 

 

Edited January 22, 2022 by rehsd

[zygot]

I love it when people create projects just because they are curious and want to know.

Question: How many LUTs were used post synthesis?

To an extent you are comparing apples to oranges since discrete LSI and MSI designs are different than LUT based programmable logic expressions.

It's been a few decades since I've had to do significant formal timing analysis for LSI/MSI board designs but there are a few things to consider for discrete logic that might be ignored in programmable logic.
- delay times for low to high transitions are different than for high to low transitions
- fanout is a big deal for discrete logic, even when using ideal connection methods. Each pin, by themselves, introduces significant capacitive and inductive loading affecting signal delay. An then there is often additional loading by termination elements. It really depends on the exact logic family input/output structure. For current based logic like ECL/PECL it was common to operate circuits at a significantly higher clock rate than formal analysis might suggest is possible.

Logic expressed in LUT based programmable logic might be quite different than how it is expressed in the source code. Back when PLA and CPLD logic was common logic actually used discrete and/nor gates.

Nonetheless, it's an interesting question, if your are curious. You can also reference family datasheets.

One way to look at this might be the process used for a logic family. Spartan 6 was fabricated on a 45 nm process. Series 7 on 28 nm and UltraScale+ on 16nm. But this might be misleading as frequently programmable logic vendors slow down clocking rates for cheaper family devices compared to other families.

[asmi]

I'd suggest to be VERY careful with combinatorial delays because there are multiple ways P&R can connect LUTs between each other and to/from IOBs, and each way can have different propagation delays. This flexibility is often useful when you need to achieve certain I/O timings. I'm not sure if it's even possible to force P&R to use a specific connection between LUTs even if you force specific placement of LUTs. Also keep in mind that FPGA were designed for syncronous (clocked) logic, so using them for purely combinatorial applications is not ideal (aside from the fact that you're wasting a ton of other resources inside FPGA). For that task it's better to use CPLDs, as a side effect, most CPLDs are "instant-on" devices, meaning whatever logic is programmed into them will take effect immediately upon powering up, while FPGA typically have a boot phase when they are not functional yet.

[rehsd]

Thanks for the info, @zygot and @asmi. I have updated the logic a bit. Below is the current logic and the LUT information from the implementation.

I'm not only comparing apples to oranges, I'm probably comparing fruits to vegetables (or worse).  :)

As far as CPLDs, is the Cmod C2 the only CPLD from Digilent? I do think the CPLD would be a better solution, assuming it's timing for basics like this are comparable. I'll have to order one to compare.

To give a little more context to what I'm trying to accomplish... I am building a 65816-based system, and for the prototyping phase, I'm looking to use an FPGA/CPLD for the address decode logic -- rather than use discrete ICs. This will provide me more flexibility in changing the decode logic without rewiring ICs. Once I finalize the logic design, I'll implement the solution with discrete ICs (e.g., the fastest 74 series of gates I can order). While the 65816 processor I am using supports 14 MHz, I expect the surrounding logic ICs will be the limiting factor to the clock speed I can run. I'm able to add up the propagation delays of the ICs, based on the data sheets. I'm trying to get a good feel for how the FPGA/CPLD will compare in timing performance. Of course, once I get things connected and running, I can check out the timings on the scope.

[rehsd]

I just stumbled across Learn.Digilentinc | Signal Propagation Delays.

"...a circuit implemented in a modern FPGA will typically have delays that are much smaller than a circuit implemented in a five-year-old FPGA, and in turn, both FPGA circuits would have far smaller delays than a similar circuit built from discrete gates."

A lot of good info in the article.