I2S pmod a/d not working

[Richm]

I have two I2S pmod boards that appear to have both failed in the same way - there is no output from the a/d converter chip ( ic2 ). I have used both for input and output with an Arty Z7 and have since moved up to a ZCU104 ( Zynq ultrascale+ 7ev MPSoC ) where I, up until recently, was using the output (d/a) section only and thus only connected the 3 (sclk, mclk, lrclk) clocks to the d/a, leaving the a/d unconnected. Wanting to use the a/d, I connected the 3 clocks and the a/d data in the Vivado block diagram and added the 4 pins to the constraints file but was getting zeros only. With an oscilloscope I was able to see an analog signal at the blocking caps (C14 & 15) but no digital signal at pin 1 of IC2, so I'm pretty sure the problem is not with my I2S RTL, block diagram or constraints.

When I was using the Arty Z7 I was always driving  the 3 clocks to both the a/d and d/a even when I wasn't using the a/d. Is it possible that I fried IC2 by using the pmod in slave mode with just the d/a connected?

This is the only thing I can think of that might have caused both to fail in exactly the way. Does anyone have any other ideas? I thought briefly about replacing the chip but there are none available from the usual suppliers.

Thank you, Rich

[JColvin]

Hi @Richm,

I am presuming you are talking about the Pmod I2S2 rather than just the Pmod I2S (since the I2S does not have a A/D converter).

On 1/13/2022 at 2:08 PM, Richm said:

When I was using the Arty Z7 I was always driving  the 3 clocks to both the a/d and d/a even when I wasn't using the a/d. Is it possible that I fried IC2 by using the pmod in slave mode with just the d/a connected?

I would like to think this is unlikely, though I can't readily say with any sort of certainty that if the clock lines were being operated outside of spec (say the MCLK on the CS5443 A/D was being run at the full 50 MHz that the CS4344 D/A can handle for example) that nothing would go wrong internally. Looking through the datasheet, there isn't any sort of registers to be manipulated so it's not like there is a "factory usage" section of internal EEPROM that you would have inadvertently changed or something like that.

Am I understanding correctly that in your Arty Z7 setup that you had the same clock sources wired to both the top and bottom row of the Pmod? Were you using both the input and the output successfully?

I'm working on getting a I2S2 project (based off of this one, https://github.com/Digilent/Pmod-I2S2) that you can test as a sanity check on the Arty Z7; the project is completed, but I don't have a Pmod I2S2 with me at home to actually verify functionality so you have known comparison point for your hardware. I'm hoping I'll get into the office tomorrow to test it.

Thanks,
JColvin

[Richm]

This is a bit embarrassing, but I discovered after buying another I2S PMOD that I wasn't driving the MCLK ( PMOD in slave mode ) at the correct frequency ratio to the LRCLK. A simple change to assign the MCLK to a different bit in the clock counter fixed the problem. This error didn't affect the D/A just the A/D thus explaining what I was observing.

In my defense I think the data sheets are a bit confusing, but rererereading them fixed the problem.