The voltage swing of the FPGA output clock is too small

[Ardelle Froeliger]

I use Xilinx Spartan3E chip to design a SDRAM data storage module, I put the global clock through ODDR2 to output a clock to the SDRAM for data reading, writing and sampling, but I found that I output this clock 80M when the voltage swing is only 500mV, the higher the frequency, the smaller the voltage swing. And I want to push the SDRAM clock to 140M, how to solve this problem?

FPGA operating conditions: BANK voltage: 3.3V

[Vivek Garg]

Hey,

 

When utilizing a Xilinx Spartan3E chip for your SDRAM data storage module, you may take the following actions to address the problem of reduced voltage swing at higher frequencies:

1. Confirm that the 140MHz clock frequency is supported by both the SDRAM and Spartan3E chip you are using. Verify that this frequency can be used by both components.

2. You can concentrate on perfecting the clock signal's routing and arrangement to increase voltage swing and signal integrity. Control the trace lengths, impedance matching, and noise coupling from other signals on the clock lines to ensure they are as noise-free as possible.

3. Modify the ODDR2 component's output buffer parameters to increase the voltage swing. To identify the ideal setup for obtaining a greater voltage swing at the specified frequency, experiment with various variables, including drive strength, slew rate, and termination.

4. Make sure the power supply for the SDRAM module and Spartan3E chip is steady and able to deliver enough current for the higher clock frequency. Reduced voltage swings and other performance concerns can be caused by an inadequate power supply.

5. Use appropriate signal termination methods to reduce signal reflections and preserve signal integrity. This can lessen any signal distortions or impedance mismatches that can affect the voltage swing.

By following these sources, you can enhance the voltage swing and improve the performance of your SDRAM data storage module when operating at a higher clock frequency.

 

Kind Regards

Vivek Garg