The voltage swing of the FPGA output clock is too small

[Ardelle Froeliger]

I use Xilinx Spartan3E chip to design a SDRAM data storage module, I put the global clock through ODDR2 to output a clock to the SDRAM for data reading, writing and sampling, but I found that I output this clock 80M when the voltage swing is only 500mV, the higher the frequency, the smaller the voltage swing. And I want to push the SDRAM clock to 140M, how to solve this problem?

FPGA operating conditions: BANK voltage: 3.3V