srath22 Posted March 5, 2021 Share Posted March 5, 2021 We are new and we are trying to implement pulpino on Arty-A7 35t FPGA board. Can any one suggest a proper flow from generation of RTL to application development ? We are using Vivado 2015.1 . Please help us to get it right. Thank You Link to comment Share on other sites More sharing options...
JColvin Posted March 5, 2021 Share Posted March 5, 2021 Hi @srath22, This probably isn't the answer you're wanting to hear, but my recommendation would be research, design, simulate, and test, with all of those steps getting repeated as necessary. Otherwise, I would recommend looking at the resources that the PULP Platform community has: https://github.com/pulp-platform/pulpino and https://pulp-platform.org/index.html. Thanks, JColvin Link to comment Share on other sites More sharing options...
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srath22
We are new and we are trying to implement pulpino on Arty-A7 35t FPGA board. Can any one suggest a proper flow from generation of RTL to application development ?
We are using Vivado 2015.1 .
Please help us to get it right.
Thank You
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