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USB104A7 DDR3 backbone clock error issue


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I'm trying to compile a design using USB104A7 board. The issue is with the DDR3L memory. It fails with the following issue.

Even after implementing the workaround suggested by Xilinx the error is the same.

[DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are MainDesign_i/clk_wiz_0/inst/clk_out1.

Clk1 -  166.667Mhz connected to sys_clk_i

clk2 -  200Mhz connected to clk_ref_i

Is there a working design that uses the DDR3L ram properly on this board. The OOB design feeds the clock directly from the on board crystal without a clocking wizard. Even following that design and adding a separate clocking wizard leads to the same issue.

Seems this comes from the hardware clock pin allocation. Any ideas how to resolve this.

 

usb104_a7.tcl

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Hi @rmccormack1,

There's an not-yet-fully-released version of the board files that helps to fix it available here: https://github.com/Digilent/vivado-boards/archive/refs/heads/Microblaze-MIG.zip

The solution is to reconfigure the MIG to accept a 100 MHz system clock (avoiding the upstream clocking wizard entirely, and just connecting the system clock to the 100 MHz clock pin) and produce it's own reference clock. This also entails constraining the sys_clk_i port in an XDC and, in the case of the USB104, either tying off the sys_reset or connecting it to a button through an inverter manually.

I've attached a working Vivado 2020.1 project.

Thanks,

Arthur

USB104A7-MIG.xpr.zip

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Posted (edited)

Hi @artvvb!, has this fix been added to any release of the board file? I am having the same error with the 1.3 version of the board files and Vivado 2021.2. Thanks!

Edit: OK, I have seen that the MIG accepts now a the 100MHz clock. Since the speed of the memory is 400 Mhz, then the ui_clk output is 400Mhz / 4 = 100Mhz. In your design, you have added an extra clocking wizard to feed the clock inputs of the Microblaze, for what reason? it isn't like connect two MCMM in series? Is related to a change of clock region?

Thanks!

Edited by pablo_gatearray
Realize of some changes
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Hi @pablo_gatearray

The additional clocking wizard was in there solely in case I wanted to tweak the clock frequency later. It's easier to change a clock frequency output by a clocking wizard than it is to run through the MIG wizard. Additionally, there are some bugs in the MIG wizard in some versions of Vivado where some settings pulled in from the PRJ files aren't necessarily visually shown in the default settings of the wizard, which makes it really easy to mess up a design when using the wizard. Using ui_clk or a ui_additional_clk to drive the Microblaze works fine, and the clocking wizard is not necessary.

Thanks,

Arthur

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