So I have setup the IP using a 200 MHz ref clock and a 40 MHz pixel clock (SVGA). This causes the IP to generates a 200 MHz serial clk. In my test bench if I try to send in the 10-bit pixel bits (using blanking signal 0101010100) one bit at a time at 200 MHz, pDataIn outputs 0100010101 and in PhaseAlign.vhd never leaves the idle state, so it doesn't seem to try the 31 "steps" to try the data at other points. Now if I adjust the rate in my testbench that I send in the bits to 200.08 MHz or to 199.2 MHz the pDataIn goes through the 31 steps, finds 0x154 16 times on pEyeSize and pAligned goes high in the end and it works and I can move onto active video signals being fed in.
Why with my testbench rate for sending in pixel bits of 200 MHz does it not seem to work, but slightly faster or slower does?
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mjrx7
So I have setup the IP using a 200 MHz ref clock and a 40 MHz pixel clock (SVGA). This causes the IP to generates a 200 MHz serial clk. In my test bench if I try to send in the 10-bit pixel bits (using blanking signal 0101010100) one bit at a time at 200 MHz, pDataIn outputs 0100010101 and in PhaseAlign.vhd never leaves the idle state, so it doesn't seem to try the 31 "steps" to try the data at other points. Now if I adjust the rate in my testbench that I send in the bits to 200.08 MHz or to 199.2 MHz the pDataIn goes through the 31 steps, finds 0x154 16 times on pEyeSize and pAligned goes high in the end and it works and I can move onto active video signals being fed in.
Why with my testbench rate for sending in pixel bits of 200 MHz does it not seem to work, but slightly faster or slower does?
Thanks,
Matt
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