DVI2RGB TB

[mjrx7]

I'm trying to setup a TB to simulate the DVI2RGB IP. I have the ref_clk setup as 200 MHz. The pixel clock I'm running at 74.25 MHz, which will generate a 371.25 MHz serial clock. I believe optimally I would want to clock in my RGB bits at the serial clock rate, but 90 degrees out of phase to place the edges of the serial clock pulse in the center of the eye of data. I'm finding however that when I match the rate of 371.25 MHz, the blanking signals never lock, but if adjust it slightly to 371.5 MHz, it'll lock and begin outputting correct data. The problem is the output skews off after a while before it comes back to correct again, which I think is being caused by the 371.5 vs 371.25 MHz pixel bit input. I've attached a picture of my data in Vivado and circled what I am talking about. Any help would be appreciated!

[elodg]

DVI is a source-synchronous digital interface where the clock sent on a dedicated lane separate from data is not directly used for sampling. DVI specifications allow for an inter-pair skew at the transmitter (!) of 20% of the pixel clock. At the receiver this increases to 60%. For practical purposes, phase of data wrt. to SerialClk and PixelClk do not matter at all. It is the responsibility of the receiver to reconstruct the SerialClk from the TMDS clock, adjust the phases of each data lane independently until it locks onto the middle of the eye, and find the pixel word boundaries in the stream of bits. IP rgb2dvi implements all this and any test bench you write should implement such functionality too.