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PMOD SD with Vivado 2020.1 & Vitis 2020.1


Sanyika

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Hello,

I have a Cmod A7 with a PmodMicroSd board, I try to run the exemple code but I get some error during the compilation
I create a basic diagram with the last pmod sd found directly from the git (clone from the git)
When I build, I get some Critical warning about Pmod but nothing block the build.

On vitis I create an empty C++ project and use the main.cc example file from the git PmodSD folder.
But when I try to compile it, I get an error (see last screenshot)

How to modify the PmodSd ip file to compile it successfully ?

 

Thank you
image.thumb.png.3e0ae1489e8d5ff3ba63cdb1efabb8a4.pngimage.png.94f981d4ea6ece08f8f5a54209be0bf8.pngimage.png.fb5df4245615284a8b474906098aa5d2.png
 

Hello @JColvin, Can you move my question on the good topic ?
Thank you

Edited by Sanyika
Wrong topic
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I use a copy of git (2020.1 branch), but Vitis don't want to compile the driver PmodSD,
I use a clone of the git because the 2 links to download the latest version doesn't works (release and fix me).

I use a second clock at 32Mhz


Do you have a copy of the last version of IPs or should I wait for the publication ?

Thank you

 

Capture.PNG

Edited by Sanyika
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Hi @Sanyika,

I apologize; the updated libraries are available here: https://github.com/Digilent/vivado-library/tree/v2020.1. I know the 2020.1 version of the Digilent Vivado library is being updated though so I'm hesitant to link to one of the branches in the tutorial.

I attempted to run this project as well in 2020.1, but got the same errors you did, so I believe the Pmod SD has not yet been updated to work with 2020.1 and Vitis (as you can see from the makefile errors in Vitis). I am not certain when it will be updated, though I do know that I successfully created and ran a Pmod SD project the other day with Vivado 2019.1.

Thank you,
JColvin

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Hello, what is the current status of this?  I'm trying to use the PmodSD with Vivado 2022.1 and Vitis 2022.1.0.  I get the following error when I try to build the System:

10:45:17 **** Build of configuration Debug for project PmodSD ****
make all 
'Building file: ../src/main.cc'
'Invoking: MicroBlaze g++ compiler'
mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/main.o" -ID:/Excalibur/excal_microblaze_test_sw/examples/fuze_ctrl_PmodSD/fuze_ctrl_wrapper/export/fuze_ctrl_wrapper/sw/fuze_ctrl_wrapper/standalone_mb_0/bspinclude/include -mno-xl-reorder -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v11.0 -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.cc"
'Finished building: ../src/main.cc'
' '
'Building target: PmodSD.elf'
'Invoking: MicroBlaze g++ linker'
mb-g++ -Wl,-T -Wl,../src/lscript.ld -LD:/Excalibur/excal_microblaze_test_sw/examples/fuze_ctrl_PmodSD/fuze_ctrl_wrapper/export/fuze_ctrl_wrapper/sw/fuze_ctrl_wrapper/standalone_mb_0/bsplib/lib -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v11.0 -mno-xl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "PmodSD.elf"  ./src/main.o   -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group
d:/xilinx/vitis/2022.1/gnu/microblaze/nt/x86_64-oesdk-mingw32/usr/bin/microblaze-xilinx-elf/../../libexec/microblaze-xilinx-elf/gcc/microblaze-xilinx-elf/11.2.0/real-ld.exe: PmodSD.elf section `.text' will not fit in region `mb_mem_ilmb_bram_if_cntlr_Mem_mb_mem_dlmb_bram_if_cntlr_Mem'
d:/xilinx/vitis/2022.1/gnu/microblaze/nt/x86_64-oesdk-mingw32/usr/bin/microblaze-xilinx-elf/../../libexec/microblaze-xilinx-elf/gcc/microblaze-xilinx-elf/11.2.0/real-ld.exe: region `mb_mem_ilmb_bram_if_cntlr_Mem_mb_mem_dlmb_bram_if_cntlr_Mem' overflowed by 22032 bytes
collect2.exe: error: ld returned 1 exit status
make: *** [makefile:50: PmodSD.elf] Error 1

10:45:20 Build Finished (took 3s.27ms)

 

Thank you.

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Hi @hthrun,

Your issue is slightly different as your design is too large for your system based on the line 2 lines above the "make: *** [makefile:50: PmodSD.elf] Error 1" that ends in "overflowed by 22032 bytes".

You would need to either reduce the size of your application and what MicroBlaze has assigned to it, or, if you happen to be using the Cmod A7 as well, you will need to add in the existing external SRAM memory to your Block Design in Vivado from the board tab. Simply having Vivado auto-connect the SRAM (it labeled as CellularRAM) should be sufficient to have alongside the rest of your design.

As for the makefile fixes, I just finished reviewing a pull request that found a fix for the makefiles (some lines needed quotation marks around some of the materials in question); I believe it should be integrated into Digilent's materials in the next few business days just kidding it only took 5 minutes, the updated Digilent Vivado Library can be found here: https://github.com/Digilent/vivado-library.

Thanks,
JColvin

Edited by JColvin
updated link
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