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How to make clear clock using clk_wiz



Hi, All


I'd like to create a frequency with an interval of 1 MHz, such as 6,7,8,9,10,11,12 MHz now.

I made it like this (attached files), but it doesn't come out properly.

When the created frequency is measured using the oscilloscope, the shaking occurs greatly.

I need a sophisticated frequency that doesn't shake. Is there a way?

Unlike the attached photo, the ENALBE I/O lock and reset were not checked.









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2 hours ago, wjdaud923 said:

I'd like to create a frequency with an interval of 1 MHz, such as 6,7,8,9,10,11,12 MHz now

I realize that there's a language barrier at work here but, excuse my being picky, frequency and interval are opposites of each other.

It sounds like you believe that your output clocks have a jitter that exceeds the 0.01 U.I specified in the clocking Wizard for the input clock. How are you measuring jitter? This is a difficult question because there are a lot of kinds of jitter. If your input clock is unstable then your output clock will be so too.

I've not had problems with FPGA derived clocks from MMCMs or PPLs. I don't see anything wrong with your settings. If you put your 100 Mhz source clock and 10 MHz clk_out1 clock into a scope and trigger on the  slower clock edge there should be 10 cycles of the faster clock for every cycle of the slower clock.

Edited by zygot
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