Hi I'm trying to get a minimal mipi csi-2 design working using the new free IP in vivado 2020.1. I have a synthisizeable design, but I'm having issues with sys_clock and mipi signals being incompatible voltages. I've been using the digilent 2019.1 pcam project as a reference, but I cant seem to find how to configure sys_clock not to interfere with the 2.5v mipi signals. I have the xdc file from the pcam demo imported into 2020.1
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs:
sys_clock (LVCMOS33, requiring VCCO=3.300) and dphy_data_hs_p[0] (LVDS_25, requiring VCCO=2.500)
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chrisn
Hi I'm trying to get a minimal mipi csi-2 design working using the new free IP in vivado 2020.1. I have a synthisizeable design, but I'm having issues with sys_clock and mipi signals being incompatible voltages. I've been using the digilent 2019.1 pcam project as a reference, but I cant seem to find how to configure sys_clock not to interfere with the 2.5v mipi signals. I have the xdc file from the pcam demo imported into 2020.1
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs:
sys_clock (LVCMOS33, requiring VCCO=3.300) and dphy_data_hs_p[0] (LVDS_25, requiring VCCO=2.500)
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