Nexys 100T Blinky tutorial error generating Bitstream

[Katherine]

Hello all, I bought the nexys 100T , and since I am new I started with the basic tutorial blinky. 
Everything goes well until I get to step 8. "Synthesis, Implementation, and Bitstream Generation"

The Synthesis ran successfully,  and where it fails is at the bitstream generation. Since the Synthesis was completed I am assuming is not the verilog code, and is just some setting that I need to complete.
The log gives the following in "Message:" (attached)

Please help this is like the most frustrating hello world I ever had to do. I attached my project files and constrain files in case anyone wants to look at it.

 

 

 

blinky.xpr Nexys-A7-100T-Master.xdc

[Gra]

Looks like you have 6 errors, but you can't see them because you have only elected to display warning..

Gra

[JColvin]

That is correct, the Errors will be what is prevented Vivado from generating the bitstream, not the Warnings.

Thanks,
JColvin

[JB_]

I have the same problem, same board - Nexys7 100T.

Here's the constraint file, omitting comments and empty lines:

set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK }];
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED }]; #IO_L18P_T2_A24_15 Sch=led[0]

This is the error I get:

[Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports CLK]'. ["C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc":8]
[Common 17-55] 'set_property' expects at least one object. ["C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc":29]

A little more info is found in the synthesis report:

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc]
WARNING: [Vivado 12-584] No ports matched 'CLK'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:7]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:7]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'CLK'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:8]
CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports CLK]'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:8]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-584] No ports matched 'LED'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:29]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:29]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [C:/UsersXXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc]
Completed Processing XDC Constraints

I'm following the instructions at https://reference.digilentinc.com/vivado/getting_started/start

I don't think they're complete, something is missing.  (I know absolutely nothing about this... which is why I bought the board, to get started with at least a blinking LED and a working flow.)

Edited June 25, 2021 by JB_

[thinkthinkthink]

3 hours ago, JB_ said:

I have the same problem, same board - Nexys7 100T.

Here's the constraint file, omitting comments and empty lines:

set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK }];
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED }]; #IO_L18P_T2_A24_15 Sch=led[0]

This is the error I get:

[Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports CLK]'. ["C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc":8]
[Common 17-55] 'set_property' expects at least one object. ["C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc":29]

A little more info is found in the synthesis report:

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc]
WARNING: [Vivado 12-584] No ports matched 'CLK'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:7]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:7]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'CLK'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:8]
CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports CLK]'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:8]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-584] No ports matched 'LED'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:29]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:29]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [C:/UsersXXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc]
Completed Processing XDC Constraints

I'm following the instructions at https://reference.digilentinc.com/vivado/getting_started/start

I don't think they're complete, something is missing.  (I know absolutely nothing about this... which is why I bought the board, to get started with at least a blinking LED and a working flow.)

XDC constraints are case sensitive, so be careful with that.

[JB_]

Ah, yes.  I think I understand.  The synthesizer collects port names from the .v sources.  It then at some point uses the constraints file to set properties on the ports.  If the case is wrong the constraints script won't find them.  Later, errors occur that prevent bitstream creation because these port properties defining pin and voltage are missing and the bitstream creator assumes the default STANDARD value and rejects it.

For some reason I thought the constraints file mapped physical properties (pin, voltage, ...) into a logical port name that's used in .v's, but clearly this is wrong.  Just mentioning this in case someone googles the problems and like me lands on this thread.  Thank you very much for your help!