Zybo Z7-10 Bring up for hello world demo

[bob_ee]

Hello Digilent

I have a project working with the Zybo Z7-10 board for an embedded PLNX application.  First step was to re-create the baseline project (hello world) to get the tool chains in place.

We worked with the project and BSP noted below to start with something that works.

However there were issues as PLNX didnt come up clean so this is a sanity check first to confirm the starting point.

So my question is this the correct project and BSP to get the hello world demo going? If not please provide a link to a complete project for the hello world demo.

 

I used Vivado 2017.4 with the Zybo Z7-10-base-linux and the Zybo Z7-10 Petalinux BSP Project .

Zybo Z7-10 Petalinux BSP Project is located here:

https://github.com/Digilent/Petalinux-Zybo-Z7-10/blob/master/README.md?_ga=2.87762640.934179241.1585861310-629904370.1584640889

which points to this Vivado project: https://github.com/Digilent/Zybo-Z7-10-base-linux.

 

 

 

[JColvin]

Hi @bob_ee,

I have moved your question to a more appropriate section of the forum.

Thanks,
JColvin

[bob_ee]

I have loaded the Zybo-Z7-10-base-linux-master project into Vivado 2017.4, run the script source ./create_project.tcl to populate files.

An error results from this step from locked  IP's.

ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'system.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
system_rgb2dvi_1_0
system_dvi2rgb_1_0
system_PWM_RGB_0
system_axi_dynclk_0_0

ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.

    while executing
"make_wrapper -files [get_files $design_name.bd] -top -force"
    invoked from within
"if {[llength $bd_list] != 0} {
  add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
  open_bd_design [glob -nocompla..."
    (file "./create_project.tcl" line 120)
update_compile_order -fileset sources_1

 

[bob_ee]

Changed tool to vivado 2017.2 , per other forum post with similar problem. Then repeated steps above with different errors shown:

open_bd_design {/home/barryr/projects/manhat/working/Zybo-Z7-10-base-linux-master/src/bd/system/system.bd}
Adding cell -- digilentinc.com:IP:PWM:2.0 - pwm_rgb
INFO: [BD 41-434] Could not find an IP with XCI file by name: system_PWM_RGB_0
ERROR: [BD 41-50] Could not find an IP with the given vlnv: digilentinc.com:IP:PWM:2.0
ERROR: [BD 41-595] Failed to add BD cell <pwm_rgb>
ERROR: [BD 41-425] Failed to read Diagram <system> from BD file </home/barryr/projects/manhat/working/Zybo-Z7-10-base-linux-master/src/bd/system/system.bd>
ERROR: [Common 17-39] 'open_bd_design' failed due to earlier errors.

 

[JColvin]

Hi @bob_ee,

I'm not a petalinux expert, so I have reached out to another engineer for their feedback. To clarify your situation though, you downloaded the release version of the BSP (github link) for the Zybo Z7-10, correct? If you are using a 2017.4 release, you should stay within the 2017.4 version of the tools toThis thread may also be of help to you if you haven't seen it already.

Thanks,
JColvin

[bob_ee]

Hello JColvin, ?

 Yes, the target HW is the Zybo Z7-10,  my SW engineer is using the Petalinux 2017.4  release and has PLNX up and running on the hardware. I am working the HW side of the project. My goal is to take a Dilignet Vivado project and re-build it and have it work with PLNX on the Zybo Z7-10. None of the HW re-builds I have done has worked error free with PLNX. I can see that tool versions are critical here and have exhausted all the try and see approaches.  I have tried several versions of Vivado building several projects with no luck.
 

Here is the path I have trying to follow.....

Zybo Z7-10 Petalinux BSP Project is located here:

https://github.com/Digilent/Petalinux-Zybo-Z7-10/blob/master/README.md?_ga=2.87762640.934179241.1585861310-629904370.1584640889

which points to this Vivado project: https://github.com/Digilent/Zybo-Z7-10-base-linux.

The readme file says that this was created for Vivado 2017.2.1 https://github.com/Digilent/Zybo-Z7-10-base-linux

Currently I am working with the Zybo-Z7-10-base-linux-master in Vivado 2017.2 with the IP problems posted above .

 I discovered a git-hub vivado-library today but not sure what version of the lib to use.

https://github.com/Digilent/vivado-library?_ga=2.45859180.934179241.1585861310-629904370.1584640889

 

So....

If this isn't the correct project to re-build for use with the Petalinux 2017.4  release then please advise what project is. 

So in summary this seems what I need to set a path forward.

1. Diligent project that maps to the Petalinux 2017.4  release.

2. Which Xilinx vivado version to open the project to re-create the project files.

3. If a Xilinx vivado tool upgade is required, what version do I upgrade to?

4. Which Vivado-library  (branch/tag) is the correct lib to resolve all the IP components for steps 2 and 3 above? 

One other question  I have is how do I convey and HW changes to the PLNX back end as it seesm the method to do this changes based on what version of the Xilinx Vivado tool is in use?

Sorry for all the words here but I need to make progress and your time is hard to come by! ?