UART interface in Zedboard

[Anji]

Hi everyone,

I am working on a project (transferring a text file containing binary value) to FPGA and receiving its o/p in text file. I am using a digilent Zedboard  and Vivado 2016.4 and I want to make a UART interface in FPGA. So far,  i have sent hardcoded i/p value in the algorithm and I can see output via SDK terminal or using teraterm. I have to test bunch of matrices so I want to make input dynamic and i thought if I can sent a text file via UART to FPGA. I have use Vivado HLS (C++) to code for my project. II want to initiate the UART interface using the C/C++ language communication between User and PS. I am a newbie and I am stuck here. How can I make UART receive the text file data and transfer it back to PC and what would be the block diagram look like? I have attached my block design. I am very confused. Any help would be appreciated, 

Thank you,

Anji

[artvvb]

Hi @Anji

The Zedboard's UART interface is part of the Zynq PS (Processing System). If you are using our board files, then it is enabled by default in the Zynq preset that gets applied through Block Automation. This means that the current design should already be able to receive UART data into the PS.

You can use the xuartps drivers in Xilinx SDK in order to receive data.

Tera Term has a menu option for transferring files (File -> Send File). The Nexys A7-100T DMA Audio demo uses a similar approach to bring in .wav files to play back through headphones or a speaker, although it uses the MicroBlaze softcore processor instead of Zynq. README, Main C file.

I have also found Python's PySerial module useful for this kind of project, as it helps avoid some of the issues that can happen with Tera Term (accidentally pressing keys, difficulty in copying and pasting out of the application). In this case, you open a port and use some straightforward read and write commands to directly send and receive bytes over the UART connection. This hackster article has some potentially useful example code.

Thanks,

Arthur