Arty s7-25 GPIO demo

[ddmdd1989]

Hello,

I am trying to walk through the GPIO demo for Arty S7-25 board on Vivado 2018.2. However, when I am trying to generate bitstream, the following error jumps out:

[DRC UCIO-1] Unconstrained Logical Port: 20 out of 20 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: BTN[3:0], LED[3:0], SW[3:0], CLK, UART_TXD, led0_b, led0_g, led0_r, led1_b, led1_g, and led1_r.

 

Any clue what causes the problem and how to possibly solve it?

Thanks in advance

[BogdanVanca]

Hello @ddmdd1989,

This error says that the ports are not connected in the XDC file. 

 

Best Regards,

Bogdan Vanca

[JColvin]

Hi @ddmdd1989,

As a confirmation check as well, the project download and Digilent board file that were used were both for the Arty S7-25 rather than the Arty S7-50?

Thanks,
JColvin

[ddmdd1989]

Yes, it is. I did not make any change to the project, and follow the steps to import the project into Vivado. Please check the attached for the screen shot. Is there any tutorial how to connect the ports in the XDC file or somewhere else I can download the project without error?

I found that most pin and ports definition in .xdc files are commented out, and I am wondering whether it is correct or not.

 

Thanks

 

 

I just found the corresponding

[ddmdd1989]

Updates:

 

I just made some changes to the .xdc file and it can be successfully built. Thanks for the help! However, I think it would be better to mention those changes in the tutorial.

 

 

[JColvin]

Hi @ddmdd1989,

I must confess that I am confused as to why you needed to make any changes. I just downloaded the release project for 2018.2 from our GitHub here, https://github.com/Digilent/Arty-S7-25-GPIO/releases, opened Vivado 2018.2, opened the Vivado project that is already included with that release, and generated the bitstream without any errors.

Based on the path name, it looks like you might've used the 2017.4 version of the project....(some time passes while I test the 2017.4 project)... yes, the 2017.4 release version does have the errors that you described. We will update the 2017.4 release project to address this error.

Thank you for pointing this out!

Thanks,
JColvin

[ddmdd1989]

I did not realize there is a release for 2018.2. Basically, I am following the steps and download the project from the following link, which I did not find any instructions on modifying the .xdc files.

https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-s7-general-io-demo/start

 

Thanks again for the help.