Migration from ISE 8.1 to vivado 19.1

[richa]

Hello folks,

I am working on zynq 7000 board in which artix 7 fpga is there.In the old design spartan 3 was used.

I am working on migration from ISE 8.1 to vivado 19.1.

I have migrated vhdl code easily but facing problem in migration of processor side.

I have created a new block design in vivado by using IP integrater with the reference of MHS file in ISE.

In ISE 8.1 block design program run from SPI FLASH which is connected to microblaze and which copy the contents from FLASH to SRAM (external memory connected to microblaze in block design).

In zynq 7000 as FLASH is towards ps side and OCM is there in zynq so I din't used external memory as well as SPI flash in block design.

My microblaze application is running but it is taking more time compared to spartan.

Delay problem was also there as in ISE they used function for delay.I have solved it out the delay problem also by hit and trial method to set the count value.Now the function Delay_mSec(100) produce same 100ms in zynq as was in spartan.

But still fucntion execution taking time in ZYNQ,

I have put led on and off between functions then I found there are two functions which is taking 16 ms in SPARTAN and 296 ms in ZYNQ.I went through those functions and found in that functions multiple functions are called which is related to FPGA -microblaze communication using GPIO port means FPGA sends the 32 signal to microblaze using GPIO port and microblaze output the signals through GPIO port to FPGA where each bit is mapped from some signals in FPGA code.

Now i am not getting that why this this much delay is there?

If anybody could help me out then it will be relaxing for me as i am struggling from 1 month.

Thanks

Here I    am attaching the block design

system.pdf

[zygot]

I have a rotary phone that I wish would have caller ID and voice recording.

ISE 8.1 is from another universe. Just learn how to use Vivado to implement the features that you need. It's not clear why you need to have a Microblaze in the PL when you have a superior ARM in the system. What board are you using?

[richa]

@zygot

zynq 7000 customize board.It's our customer application which was on spartan previously .Now the complete design has migrated to ZYNQ  so I have the work to migrate the spartan design onto zynq.I can not modify their design .I have done it .problem I am facing regarding function execution 

 

[Gra]

Hello Richa,

I've flipped designs between different FPGA families many times, its not as simple as it first appears, as I guess you know it can be a real can of worms.

Id be looking for issues in the following areas...

 

You talked about changes to the memory where the program runs from, I'd re-visits that.

If you've changed from a Spartan3 to an Artix 7 you will need to update your VHDL to make it work efficiently on the new architecture.  If you miss this step (at best) it can under perform (at worst) the design may behave completely differently on the new device, so I'd be checking for issues here too.

If you moved from ISE 8.1 I think you will have changed the bus structure from a PLB to AXI, I'd be looking for problems there.

I'd also have a conversation with the customer about exactly what can't be changed and why that is. You may be able to do a better job for them and save them some money, if they can be a little more flexible. Sometimes a partial re-design is a better option. As Zygot said "from another universe" well at lest from another time ... they are very different tools and very different devices. 

Hope that's helpful Gra

[richa]

@Gra Thanks for your polite reply..

I can understand that it's not easy as we think.But everything is perfect expect the  function execution.

yes IN SPARTAN 3 PLB bus was there now AXI bus.

but there is no solution to deal with it?