Alonso Posted March 31, 2019 Share Posted March 31, 2019 Hello. I'm trying to simulate SRAM to DDR component from Nexys 4 DDR, I'm using Vivado 2017.2 and i want to write on DDR. I have respected timming about all entrande signals (RAM) but i never write on DDR, I always see 'ZZZZ' at ddr2_dq signal. Here is a screencapture about simulation. What am i doing wrong? Thank you. Link to comment Share on other sites More sharing options...
jpeyron Posted April 1, 2019 Share Posted April 1, 2019 Hi @alonzo, Welcome to the Digilent Forums! Are you assigning initial values I.E. 0 or 1 for the signals that are interacting with the project? Here is a project that i believe uses the SRAM to DDR component for the Nexys 4 DDR. Here is the reference manual for the SRAM to DDR component. best regards, Jon Link to comment Share on other sites More sharing options...
Alonso Posted April 6, 2019 Author Share Posted April 6, 2019 TOP.vhd Here is my TOP module and the testbench, i think that i am assigning initial values. Thank you. TOP_TB.vhd Link to comment Share on other sites More sharing options...
jpeyron Posted April 11, 2019 Share Posted April 11, 2019 Hi @Alonso, Here is a forum thread that deals with simulation of the SRAM to DDR component. Is there a specific issue with the SRAM to DDR component you are concerned about? best regards, Jon Link to comment Share on other sites More sharing options...
Alonso Posted April 30, 2019 Author Share Posted April 30, 2019 I dont know what happend, but i cant simulate it. Can it be simulate?? or have i to use FPGA? thank you Link to comment Share on other sites More sharing options...
jpeyron Posted May 2, 2019 Share Posted May 2, 2019 Hi @Alonso, I have not simulated the SRAM to DDR component but I have used it in multiple projects. Here is the legacy tutorial getting started with microblaze that uses the SRAM to DDR component. best regards, Jon Link to comment Share on other sites More sharing options...
Alonso Posted May 9, 2019 Author Share Posted May 9, 2019 Thank you for your answers. Look that, i simulate the "music looper" project which you told me. And i see that the state (nstate) of SRAM to DDR component never change: And the signal calib_complete, always is X. Thank you. Link to comment Share on other sites More sharing options...
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