Alonso Posted March 31, 2019 Share Posted March 31, 2019 Hello. I'm trying to simulate SRAM to DDR component from Nexys 4 DDR, I'm using Vivado 2017.2 and i want to write on DDR. I have respected timming about all entrande signals (RAM) but i never write on DDR, I always see 'ZZZZ' at ddr2_dq signal. Here is a screencapture about simulation. What am i doing wrong? Thank you. Link to comment Share on other sites More sharing options...
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