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Can not simulate SRAM to DDR component


Alonso

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Hello.

I'm trying to simulate SRAM to DDR component from Nexys 4 DDR, I'm using Vivado 2017.2 and  i want to write on DDR. I have respected timming about all entrande signals (RAM) but i never write on DDR, I always see 'ZZZZ' at ddr2_dq signal. 

Here is a screencapture about simulation. What am i doing wrong?

Thank you.

image.thumb.png.de91d1aa0145e18805144fa014043148.png

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  • 3 weeks later...

Thank you for your answers.

Look that, i simulate the "music looper" project which you told me. And i see that the state (nstate) of SRAM to DDR component never change:

image.thumb.png.f6c855906f13e872eb16efa1525e82b9.png

And the  signal calib_complete, always is X.

Thank you.

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