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To build an AXI-lite peripheral


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If you've followed the Vivado tutorial to build an AXI-lite peripheral, you'll know to ask Vivado to generate an IP core for you which you can then edit to your taste.

What's not so commonly known is that this core has bugs in it : it does not comply with the AXI standard.  Specifically, if the Vivado demonstration core receives two requests in a row while the return channels ready line is low, one of those two requests will get dropped.  This applies to both read and write channels.  The failure is so severe that it may cause a processor to hang while waiting for a response.  Worse, since this is caused within vendor provided code, most users won't see any need to examine it, instead choosing to believe that their own code must somehow be at fault.

The article demonstrates the bugs in the 2016.3 AXI-lite demonstration core.  Since that Vivado 2016.3, Xilinx has updated their AXI-lite demonstration to add another register to its logic--presumably to fix this issue.  As of version 2018.3, even this updated logic continues to fail verification.

Should you wish to repeat this analysis, this same article discusses how it was done.  Only about 20 lines of logic need to be added to any Verilog AXI-lite core, plus the lines necessary to instantiate a submodule containing a property file.  That's all it takes to verify that any AXI-lite core properly follows the rules of the road AXI-lite bus using SymbiYosys--a formal verification tool.  The steps necessary to correct this logic flaw are also discussed.

Since writing that article, I have posted another basic AXI-lite design which doesn't have these flaws.  Moreover, the updated design can process bus transactions with a higher throughput than the original design ever would.  While I'm not sure quite how fast MicroBlaze or even the AXI interconnect can issue bus requests, this design at least shows how you could build a slave peripheral that can handle two requests at once.

Feel free to try it out and let me know if you find any flaws within it.


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