zygot Posted September 27, 2018 Share Posted September 27, 2018 Even some of us who think of ourselves as fairly competent FPGA developers can get confused as to what's really taking place when we write our source HDL, create a bitstream, and simulate ( when we need to debug the hardware ) what we think ( the 'what we think' as opposed to 'what is' being the crux of the matter ) our FPGA and connected IO are doing. The case for making simulation a core part of the design process has been made elsewhere so this thread will deal with the large gap between reality and our limited ability to model reality effectively. Simulation is not an Oracle that magically understands all physical behaviors and identifies and reveals problems or deficiencies in our HDL code for solving every aspect of a particular interface. It's easy, while focused on unwanted behaviors in our hardware, to forget about all of the variables involved in generating a configuration file. For now, let's forget about errors in timing, errors in RTL design and errors in grasping what might be happening in the physical realm of our logic and IO interfaces. Depending on the setting of our tools ( synthesis, placer and route, etc ) what gets expressed in the configuration of the FPGA might not resemble our source code. Hopefully it provides the desired behavior for every condition that we need it to. Having this is mind during simulation is foundational. Fortunately, FPGA vendors offer support for simulators in helping close the gap between what we think our source code is trying to express and what the FPGA has been configured to do given the state of various inputs. This is where timing simulation comes into play. You can tell ISE or Vivado to create an SDF netlist of the optimized, synthesized, placed and routed logic as it will exist in the FPGA. As your designs get more complex timing simulation gets to be more of a requirement. For a long time ModelSim was the only real simulator option around. Of course there's never been one version of ModelSim for FPGA development. Each vendor worked with ModelSim to allow simulating the details of it's device architectures. So, you might have found the 'free' version of ModelSim provided by Xilinx or Altera to be adequate for basic RTL simulation. But if you produced FPGA based products then you soon learned that you had to spring for the very expensive paid 'full' version of Altera ModelSim or Xilinx ModelSim. You could also buy ModelSim from Mentor for a particular FPGA device family. Altera and a few other FPGA vendors still rely on ModelSim to provide the basic simulator framework. Xilinx, for a long time now has gone its own way with ISIM or XSIM. I know one guy who swears by free third party simulation tools as a better choice for all of those very expensive simulator company or vendor simulator options. I've been using, off and on the very expensive simulators and 'free' vendor simulators for over 3 decades now and I'll need some compelling proof that open source or free tools are an adequate replacement for them. I've worked for a lot of companies making FPGA based products and none of them rely on such tools. In fact I;ve never come across any that use them as optional development aids. Simulation is such a complicated topic that I do hope that this thread generates some interesting observations, thoughts, and opinions from a wide range of practitioners. So far, I haven't even alluded to most of the interesting aspects of FPGA simulation. VHDL and Verilog are languages designed to do much more that logic simulation but let's keep this thread to that sphere. Link to comment Share on other sites More sharing options...
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