I am trying to implement a design in ISE using the RAM2DDR_REF_Component. I get the following error at the MAP stage. I used both the Nexys4DDR.ucf and the mig.ucf files to constrain the design. Any help would be much appreciated.
ERROR:Place:897 - The following IOBs have been locked (LOC constraint) to the I/O bank 34. They require a voltage reference supply from the VREF pin(s) within the same I/O bank to be available. The following VREF pins are currently locked and can't be used to supply the necessary reference IO Standard: Name = SSTL18_II, VREF = 0.90, VCCO = 1.80, TERM = NONE, DIR = BIDIR, DRIVE_STR = NR List of locked IOB's: ddr2_dq<2> ddr2_dq<1> ddr2_dq<4> ddr2_dq<3> ddr2_dq<15> ddr2_dq<0> ddr2_dq<9> ddr2_dq<6> ddr2_dq<5> ddr2_dq<8> ddr2_dq<7> ddr2_dq<10> ddr2_dq<11> ddr2_dq<12> ddr2_dq<13> ddr2_dq<14> ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
Question
Anding
Hello,
I am trying to implement a design in ISE using the RAM2DDR_REF_Component. I get the following error at the MAP stage. I used both the Nexys4DDR.ucf and the mig.ucf files to constrain the design. Any help would be much appreciated.
ERROR:Place:897 - The following IOBs have been locked (LOC constraint) to the
I/O bank 34.
They require a voltage reference supply from the VREF pin(s) within the same
I/O bank to be available.
The following VREF pins are currently locked and can't be used to supply the
necessary reference
IO Standard: Name = SSTL18_II, VREF = 0.90, VCCO = 1.80, TERM = NONE, DIR =
BIDIR, DRIVE_STR = NR
List of locked IOB's:
ddr2_dq<2>
ddr2_dq<1>
ddr2_dq<4>
ddr2_dq<3>
ddr2_dq<15>
ddr2_dq<0>
ddr2_dq<9>
ddr2_dq<6>
ddr2_dq<5>
ddr2_dq<8>
ddr2_dq<7>
ddr2_dq<10>
ddr2_dq<11>
ddr2_dq<12>
ddr2_dq<13>
ddr2_dq<14>
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
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