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Modifying BRAM initial value quickly



I'm using two inferred RAM modules which are assigned an initial state by reading lines from a file, as suggested to me previously here, in VHDL. The setup works fine, and all the RAM contents are loaded during synthesis properly.

However, as my design is pretty large, it takes a lot of time to synthesize the project each time I need to only change the RAM initialization files. I need to synthesize very often while testing with different memory contents, my design being otherwise the same. Is there a way to only modify the memory contents of a design without having to synthesize the whole project? I tried using incremental builds but the improvement was not that effective.

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Hi ntrstd11,

For Vivado, this almost understandable Answer Record http://www.xilinx.com/support/answers/53732.html might be of help.

For ISE, DATA2MEM is what you want to use (http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/data2mem.pdf)

For inferred memory blocks, you sometimes need to use the floor-planning tool to work out what the BRAM instance names are. It might be a wise time to switch over to using primitives, where you can be sure that the naming will stay consistent and they won't be optimized out.


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The initial value is stored as a bunch of properties. You can load the design into Vivado, use set_property to modify the initial values, and then generate a new bitstream without doing any other steps.

I have done this sort of thing with MMCM to modify generated clock frequencies, but have not done it with BRAMs. However, the principal is the same so I expect it to work.


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