I am trying to use SRAM to DDR Component which i've downloaded from nexys4-ddr-sram I've downloaded the UCF file for ddr pinout and added it to existing Nexys4DDR-Master.ucf at the end.
I've created a instance of ramddr2xadc component and i've added IOs like switches and buttons.
I started Translate and Map, Translate returned a lot of messages like:
WARNING:ConstraintSystem:119 - Constraint <NET "sw<0>" LOC=J15 |> [Nexys4DDR_Master.ucf(13)]: This constraint cannot be distributed from the design objects matching 'NET "sw<0>"' because those design objects do not contain or drive any instances of the correct type.
And Map returned:
ERROR:MapLib:979 - LUT6 symbol "Mmux_ram_addr[26]_ram_addr[26]_mux_10_OUT_B11" (output signal=Mmux_ram_addr[26]_ram_addr[26]_mux_10_OUT_B1) has input signal "btnr" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven.
I found there http://www.xilinx.com/support/answers/34900.html a solution so i turned on the "Add IO Buffers" option. (I also tried to create instances of buffers and the result was the same).
It removed these errors but now Map returned different error:
ERROR:Place:897 - The following IOBs have been locked (LOC constraint) to the I/O bank 34. They require a voltage reference supply from the VREF pin(s) within the same I/O bank to be available. The following VREF pins are currently locked and can't be used to supply the necessary reference IO Standard: Name = SSTL18_II, VREF = 0.90, VCCO = 1.80, TERM = NONE, DIR = BIDIR, DRIVE_STR = NR List of locked IOB's: ddr2_dq<2> ddr2_dq<1> ddr2_dq<4> ddr2_dq<3> ddr2_dq<15> ddr2_dq<0> ddr2_dq<9> ddr2_dq<6> ddr2_dq<5> ddr2_dq<8> ddr2_dq<7> ddr2_dq<10> ddr2_dq<11> ddr2_dq<12> ddr2_dq<13> ddr2_dq<14>
I am using the ngc file from the /Netlist directory but i also tried to use files from /Source and i had the same problem. The solution for this issue on Xilinx Support tells me that i need to correct pin-out but I have downloaded official component so i think that it should work without any modifications.
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BlazeMicro
Hello,
I am using Xilinx ISE 14.7
I am trying to use SRAM to DDR Component which i've downloaded from nexys4-ddr-sram
I've downloaded the UCF file for ddr pinout and added it to existing Nexys4DDR-Master.ucf at the end.
I've created a instance of ramddr2xadc component and i've added IOs like switches and buttons.
I started Translate and Map, Translate returned a lot of messages like:
And Map returned:
I found there http://www.xilinx.com/support/answers/34900.html a solution so i turned on the "Add IO Buffers" option. (I also tried to create instances of buffers and the result was the same).
It removed these errors but now Map returned different error:
I am using the ngc file from the /Netlist directory but i also tried to use files from /Source and i had the same problem.
The solution for this issue on Xilinx Support tells me that i need to correct pin-out but I have downloaded official component so i think that it should work without any modifications.
Could someone help me with this issue?
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