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Found 6 results

  1. Hey, I am using Cortex M1 soft core processor on Arty A7 100T using Vivado 2020.1 and successfully generated bitstream for simple AXI-Uartlite project and exported hardware xsa file, but when i tried to create a Application Project for the same using xsa file in Vitis 2020.1 the platform is getting created but the basic c/c++ application project creation is giving error as "Failed to call GENERATE_APP". Below is the Vitis log file for that error. Can someone help in debugging this error? Thanks 13:51:28 DEBUG : Registering SDKStatusHandler to handle trace exceptions. 13:51:28 DEBUG : Registered the core plugin as the backup plugin for storing repository paths. 13:51:28 INFO : Launching XSCT server: xsct.bat -n -interactive D:\FPGA_Projects\Workspace\temp_xsdb_launch_script.tcl 13:51:28 INFO : XSCT server has started successfully. 13:51:28 INFO : Registering command handlers for Vitis TCF services 13:51:29 INFO : plnx-install-location is set to '' 13:51:29 INFO : Successfully done setting XSCT server connection channel 13:51:29 INFO : Successfully done query RDI_DATADIR 13:51:29 INFO : Successfully done setting workspace for the tool. 13:51:29 INFO : Restoring global repository preferences: C:\Users\vybha\Documents\AT472-BU-98000-r0p1-00rel0\vivado\Arm_sw_repository 13:51:31 INFO : Platform repository initialization has completed. 13:52:35 INFO : Result from executing command 'getProjects': Microblaze_uart_wrapper;arty_uart1_wrapper;arty_uart_wrapper;arty_uart_wrapper_1;arty_uart_wrapper_2;cortex_m1_uart_wrapper;design_1_wrapper;mblz_uart_gpio_wrapper;mblz_uart_gpio_wrapper_1;mblz_uart_gpio_wrapper_2;zynq_uart_wrapper 13:52:35 INFO : Result from executing command 'getPlatforms': Microblaze_uart_wrapper|D:/FPGA_Projects/Workspace/Microblaze_uart_wrapper/export/Microblaze_uart_wrapper/Microblaze_uart_wrapper.xpfm;arty_uart1_wrapper|D:/FPGA_Projects/Workspace/arty_uart1_wrapper/export/arty_uart1_wrapper/arty_uart1_wrapper.xpfm;arty_uart_wrapper_1|D:/FPGA_Projects/Workspace/arty_uart_wrapper_1/export/arty_uart_wrapper_1/arty_uart_wrapper_1.xpfm;arty_uart_wrapper_2|D:/FPGA_Projects/Workspace/arty_uart_wrapper_2/export/arty_uart_wrapper_2/arty_uart_wrapper_2.xpfm;arty_uart_wrapper|D:/FPGA_Projects/Workspace/arty_uart_wrapper/export/arty_uart_wrapper/arty_uart_wrapper.xpfm;design_1_wrapper|D:/FPGA_Projects/Workspace/design_1_wrapper/export/design_1_wrapper/design_1_wrapper.xpfm;mblz_uart_gpio_wrapper_1|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper_1/export/mblz_uart_gpio_wrapper_1/mblz_uart_gpio_wrapper_1.xpfm;mblz_uart_gpio_wrapper_2|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper_2/export/mblz_uart_gpio_wrapper_2/mblz_uart_gpio_wrapper_2.xpfm;mblz_uart_gpio_wrapper|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper/export/mblz_uart_gpio_wrapper/mblz_uart_gpio_wrapper.xpfm;zynq_uart_wrapper|D:/FPGA_Projects/Workspace/zynq_uart_wrapper/export/zynq_uart_wrapper/zynq_uart_wrapper.xpfm 13:52:35 INFO : Platform 'cortex_m1_uart_wrapper' is added to custom repositories. 13:52:36 ERROR : Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. 13:52:36 ERROR : java.lang.RuntimeException: Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. at com.xilinx.sdk.xsdb.XsdbCommandUtils.handleResult(XsdbCommandUtils.java:387) at com.xilinx.sdk.xsdb.XsdbCommandUtils.executeAndRespond(XsdbCommandUtils.java:325) at com.xilinx.sdx.sdk.core.gen.CTemplateGen.generate(CTemplateGen.java:105) at com.xilinx.sdx.sdk.core.gen.CppTemplateGen.generate(CppTemplateGen.java:53) at com.xilinx.sdx.sdk.core.gen.StandaloneProjectHandler.createCoreApp(StandaloneProjectHandler.java:93) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createApplication(AppCreationHandler.java:79) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.execute(AppCreationHandler.java:69) 13:52:36 ERROR : Failed to create application project org.eclipse.core.runtime.CoreException: Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. at com.xilinx.sdx.sdk.core.gen.StandaloneProjectHandler.createCoreApp(StandaloneProjectHandler.java:150) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createApplication(AppCreationHandler.java:79) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.execute(AppCreationHandler.java:69) at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.executeInternal(SdkAppCreationHandler.java:75) at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.lambda$1(SdkAppCreationHandler.java:67) at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2289) at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2311) 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references'
  2. Hello, I hope you will be enjoying your vacations if you have been given some. For me this has meant finally being able to work on my spare-time experiment and finally reach closure on my upgraded design. Let me describe the process. The ArtyZ7-20 is just the initial prototyping. I'm going to move to real production FPGA boards ASAP (probably in August) but for the time being I'd just want to go ahead with the Arty. The system is systemverilog RTL and barebone C++. The initial design was 100Mhz and 6-stage pipe. Vivado estimated about 2.2W power. I suspect it was much lower than that. I ran it over USB2. Let me be clear my mainboard has a fairly beefy usb2 going beyond usual specification. I later went ahead with a 12-stage pipeline. I was unable to run it on USB2, but it runs rock stable on USB3. In the last few weeks I've upgraded it to 200Mhz. Vivado now estimates 5.5W. I never expected this to be able to run on USB3 power (I haven't tried, but I doubt my USB3 can deliver 1A) so I've hooked the ARTY through its power jack to a industrial supply (details, if needed, in a later message) The board gives up. If I leave the board free-running, it hangs almost instantly. Here's how it goes by stepping it in the debugger: Booting ok, DHCP fails (ok) and fixed ip is estabilished. Server correctly found, input requested and correctly received. Input feed to PL PL start As soon as I pass beyond the {4} breakpoint, the card hangs. The debugger will never hit the next breakpoint. I can tell the thing is more relevant than just software because my PL turns on red LD5 when idle. It would turn on green and eventually blue plus animate LD0-3. This never happens. I was thinking about hooking a bunch of capacitors to the supply and see if it improves but I guess there might be other issues to consider as well. Do you have any suggestion?
  3. I am a newbie to FPGA and all things related. I installed all the board files from the repository. Created my block design and ran the block automation. I created a HW platform and a SW application with the template. I put my Zybo Z7 10 on JTAG mode. i can verify that the UART prints out data when it passes a print statement. But the printed value doesnt correspond to what is supposed to be in it. I have attached necessary screenshots. I am guessing that i have an error with the UART. To make sure my cable wasnt at fault, I reset the system to get the OOB image "initializing init:done ..". Both the Tera term and the vitis terminal gave the same output. VIvado version 2020.2 OS: Windows 11 Thanks in Advance.
  4. Hi, I had tried using the Pmod MTDS to build some simple projects by using the microblaze with Arty A7-35T. I had followed the "Getting Started with Digilent Pmod IPs" tutorial. The bitstream file was successfully generated and exported to the VITIS 2020.1. After I created an application project in the VITIS 2020.1, I copied the main.cc and MyDispDemo1.cc into the src folder as requested after read the README.txt. However, when I started to build the project, it failed. It seem like missing the library files for the MyDispDemo.cc. I had tried many methods, rebuild it, and try to export the bitstream file again to the VITIS 2020.1. However, the problem still exist. So, is there any steps I miss out? Kindly need some helps in order to make the Pmod MTDS works with the microblaze by using the Arty A7-35T. Thank you very much.
  5. Hi, I trying to build some project by implement the PMOD MTDS using microblaze on Arty A7-35T. I had followed the instructions in the README.txt of PMOD MTDS and the microblaze ip core with the PMOD MTDS ip core is successfully built with bitstream file successfully generated. However, when built the project using VITIS 2020.1, it failed. It show that "undefined reference to mydisp". When I open up the folder, it seem liked the "stdint.h" library file is not recognized by the compiler. Kindly need help on this kind of problem. Thanks.
  6. Hi Im using Zybo 7020 Vivado/Vitis 2020 and i have some errors on Vitis when i compile the hw platform. "Running Make libs in ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src" make -C ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta rtfiles -g -Wall -Wextra" make[2]: Entering directory 'C:/Users/NZT/workspace/Gyrotest/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src' "Compiling PmodGYRO..." arm-none-eabi-ar: *.o: Invalid argument make[2]: *** [Makefile:19: libs] Error 1 make[1]: *** [Makefile:30: ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src/make.libs] Error 2 make: *** [Makefile:30: zynq_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a] Error 2 make[2]: Leaving directory 'C:/Users/NZT/workspace/Gyrotest/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src' make[1]: Leaving directory 'C:/Users/NZT/workspace/Gyrotest/zynq_fsbl/zynq_fsbl_bsp' Building the BSP Library for domain - standalone_domain on processor ps7_cortexa9_0 "Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_7/src" "Compiling gpiops" "Running Make libs in ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src" make -C ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta rtfiles -g -Wall -Wextra" "Compiling PmodGYRO..." arm-none-eabi-ar: *.o: Invalid argument make[1]: *** [Makefile:19: libs] Error 1 make: *** [Makefile:30: ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src/make.libs] Error 2 Failed to build the bsp sources for domain - standalone_domain Failed to generate the platform. Reason: Failed to build the zynq_fsbl application. invoked from within "::tcf::eval -progress {apply {{msg} {puts $msg}}} {tcf_send_command tcfchan#0 xsdb eval s es {{platform active Gyrotest; platform generate }}}" (procedure "::tcf::send_command" line 4) invoked from within "tcf send_command $::xsdb::curchan xsdb eval s es [list "platform active $PLATFORM_NAME; platform generate $target"]" invoked from within "if { $iswindows == 1 } { set XSDB_PORT [lindex $argv 0] set PLATFORM_NAME [lindex $argv 1] set arglen [llength $argv] set lastind..." (file "C:/Xilinx/Vitis/2020.1\scripts\vitis\util\buildplatform.tcl" line 11) I thinks there is some problems in the makefile the error comes from this line in makefile $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} I downloaded the Library from github
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