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Showing results for tags 'spartan3e'.
Hello everyone, So I own a Basys 2 board with spartan 3E FPGA and I am using ISE Design Suite 14.5. I want to create a VGA output with 800x600 resolution and 40Mhz clock so it will have 60Hz refresh rate. I am writing the code in verilog. I have entered exact numbers for horizontal counter, vertical counter, hsync and vsync that are required for operation stated above. However, I am unable to output the VGA signal. I am using two DCMs that can be generated in the ISE design suite, I am using first DCM to multiply 50MHz clk to 100Mhz and then I am using second DCM to divide 100Mhz with 2.5 to get 40Mhz clk frequency. I tried many combinations of DCM properties (like setting external clkin and internal, changing feedback properties etc.) but was not successful. I am uploading the whole code directory archived in a Winrar, so you can also maybe replicate the issue. Any help is appreciated! Thanks in advance. lab9v360hz.rar