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  1. Hello everyone, So I own a Basys 2 board with spartan 3E FPGA and I am using ISE Design Suite 14.5. I want to create a VGA output with 800x600 resolution and 40Mhz clock so it will have 60Hz refresh rate. I am writing the code in verilog. I have entered exact numbers for horizontal counter, vertical counter, hsync and vsync that are required for operation stated above. However, I am unable to output the VGA signal. I am using two DCMs that can be generated in the ISE design suite, I am using first DCM to multiply 50MHz clk to 100Mhz and then I am using second DCM to divide 100Mhz with 2.5 to get 40Mhz clk frequency. I tried many combinations of DCM properties (like setting external clkin and internal, changing feedback properties etc.) but was not successful. I am uploading the whole code directory archived in a Winrar, so you can also maybe replicate the issue. Any help is appreciated! Thanks in advance. lab9v360hz.rar
  2. Hi All, Its been a while in setting up Compilers and Synthesizers. No problem setting up the Spartan 3E 1600 it was on the list in ISE 14.7. However, the SpartanĀ®-3 FPGA Starter Kit board has a four-character, seven segments LED display controlled by Spartan 3 FPGA is not on the list. What would it take to build up a library or configuration in ISE 14.7 . to select this Spartan 3 Board. Characteristics the compiler needs Chip and Package number as well as the Temp Code, maybe. Most importantly it needs to know where Jtag is and how it's connected. RAM and ROM chips and addresses going to the FPGA. There is a place for New and Old Starter Kits. However, that has failed to work plus Xilinx has no way of knowing where the ROM and RAM not unless I share this in the UCF file. The data sheet has the DRAM not sure if the PROM is list or JTAG I am not sure how to set this up. I have the User Guide here. No real instructions on how to build this list of custom or pre-bought boards for the ISE 14.7. The error I am getting is program failed to load. Any help would be appreciated! Phil