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Showing results for tags 'ram2ddr'.
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Hi, I am writing a systemverilog controller for read and write to ft313 chip internal memory. Kindly help me on whether i can use pmod for the external interface which consists of 16 bit bidirectional data, 8bit address bus, chip select, read and write signal. with outputs defined as reg, Do i have to use bram specifically or it is taken care if defined as reg.
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I am trying to setup DDR2 using the Xilinx Memory Interface Generator using Vivado 2017.2 for the Nexys 4 DDR board. I am currently at the stage were I am prompted to select Pin/Bank Selection Mode: 1. New design: Pick the optimum banks for new design 2. Fixed Pin Out: Pre-existing pinout is known or fixed I am not sure what to choose. I have seen a lot of web forums that suggest using the second option and downloading the MIG ucf file. I tried this method but the Xilinx Memory Interface Generator in Vivado 2017.2 keeps crashing after I select the second option. Any assistance would be highly appreciated.
