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Dear All, "I'm working with Vivado 2018.3 and a Zybo Z7020 board" I write here because I have a very strange problem in a project that I have been developing in the past months. Namely, I've been writing a verilog code to run on a Z7020 board. This code takes user input as parameters (that are hence hard-coded) and everything works fine with this project (no errors or not understandable warnings...) Now, my job is to make sure that these so-colled parameters can be changed through a serial connection from a laptop. Hence, I've packaged my module in an IP and connected it to the PS, programmed the SDK and here is the problem : Many things work but some don't. At the beginning, I thought that the SDK used a different convention to represent signed integers (two complement, only first bit changed...) and have thereby checked that the parameters sent by the SDK where equal to hard coded values in the PL... and they are! Every single bit.. I'm now out of option to understand my problem... Has anyone had similar issues in the passt? Does anyone have a clue for me? Thank you a lot, P.S. : Please do not hesitate to write a comment if you need any further infos.
Dear all, I'm using Vivado 2018.3 and a Zybo Z7010 board. I have finally finished my project (I actually owe this forum much), and I am now trying to use the board without having to open nor Vivado neither the SDK. Basically, I know that I can program the QSPI flash memory of the board so that the program can run without having to upload it. How this works is still unclear, is switching from JTAG to QSPI enough or should I do something on Vivado? However, I am also using the Zynq processor which runs an application that I start from the SDK. Can I avoid opening the SDK? The better thing would be if I could programm the FPGA through Matlab but I don't know if this is possible. Could you point me to some tutorials or the matlab functions (if they exist...). Thank you very much, NotMyCupOfTea