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Found 4 results

  1. Myself Ashika. I'm working as an ASIC Engineer at AHEESA DIGITAL INNOVATIONS. We have purchased the product JTAG HS3 Programming Cable in Digikey. We are facing a problem in running the Digilent Adept Runtime , Utilities and Plug-in Softwares for Xilinx ISE 14.7 i.e, being used for JTAG connection. I have tried installing it but there is no permissions to access (read or write) the files which is available in the Digilent Adept SDK tar file. The programming cable is getting detected after giving the cable autoconnect option in IMPACT. But the program is getting failed and also there is an error : "INFO:iMPACT - Current time: 13 Jul 2022 22:22:34 PROGRESS_START - Starting Operation. INFO:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '1': Device IDCODE : 00001111111111111000111111111111 INFO:iMPACT:1579 - '1': Expected IDCODE: 00000110111000011000000010010011 PROGRESS_END - End Operation. Elapsed time = 0 sec." We need some suggestions about this problem. Is there any other ways to overcome this problem ?
  2. Hi, I am trying to program RFSoC2x2 board by Xilinx (Running PYNQv2.7) with XUP USB-JTAG programming cable (https://digilent.com/shop/xup-usb-jtag-programming-cable/) using Vivado 2020.1.1 on Windows 10 but I am being unable to install cable drivers for the cable. I followed the procedure mentioned by one of your employee on Digilent Forum: https://forum.digilent.com/topic/13275-xup-usb-jtag-programmer/ but it doesn't seem to be working for the combination of OS and software version I have mentioned above. Can you please confirm whether cable works for the Vivado 2020.1.1 on windows 10 for Xilinx RFSoC2x2 board? Hereby attaching the screenshots from the procedure I followed for installing cable drivers:
  3. I need to use the JTAG header to program the Zedboard, since the MicroUSB connector is physically damaged. I cannot find any documentation or forums about how to use the JTAG connector for programming the FPGA, so I am going to ask for your help. I have a basic design in Vivado for making switch 0 toggle led 0. The bitstream is ready to be sent to the FPGA. However, when I try to connect to the hardware, by clicking "Open target", it is unable to connect. When I try to manually connect: I am using Xilinx Platform Cable USB adapter for connecting the JTAG to the computer's USB input: I have the driver installed, and it appears in my list of devices when plugged in, and disappears if I unplug it, and is up-to-date: I suspect the jumpers may not be configured properly? But again I cannot find clear documentation on how to set this up. This is how mine is set up: Here is some information about my computer: I am using Vivado 2016.1, since that is used in a lot of the tutorials. I think the Diligent tutorial uses 2016.2. It also comes with the Zedboard board file, although I downloaded the one made by Diligent as instructed in the tutorial. I hope I have provided enough information. I appreciate any help!
  4. Hi, First thing first. I am a starter in the fpga custom design. I have done few simple projects codes in Digilent virtex 5 board but now circumstances requires me to get more IO pins. I will, in this section mention first what I am planning (English is not my first language sorry for any errors). 1) I am using XC6SLX9 2) Route the VCCAUX, VCCINT, GND, 100MHZ single ended clk. 3) Route out the JTAG pins (namely TMS, TDO, TDI, TCK) 4) I am using ISE 14.7 5) 1) I just want to generate gate signals. In this section I shall lay out what help I want. 1) Is what I have done enough to program the spartan 6 device via JTAG? (I know it will be volatile) 2) Can I program it using the JTAG HS3 cable? (someone said that I need the platform cable to program and HS3 only works with series 7 ics, but platform cable would cost too much for me at this moment) 3) For a 14pins (7 pins in 2 row) JTAG connector, what other routing I need to consider from the FPGA (except the 4 JTAG pins mentioned in the previous section) . Any other help or information that I need is extremely acknowledged. FYI: I am also attaching an approximate final outcome that I want.
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