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Found 7 results

  1. Hello everyone! I wanted to challenge myself and I tried implementing an I2C master capable of configuring SSM2603. I've been so far unsuccessful, not even an ACK shows up when attempting a read. Here's the wave I'm generating (I'm trying to read reg 0x6) compared with the phases as described in the datasheet. They look the same both in Post-implementation timing simulation and when checking the probes. The ACKs from master side A(M) and ~(A(M) are given unconditionally for the time being. Question 1: do you see any issue here? Question 2: The tool infers OBUFT for ac_sda and OBUF for ac_scl, but I get this warning, is it important? Question 3: lastly, do I still have to generate other signals like MCLK, BCLK, PBLRC and so on to be able to read registers over I2C? As you can see from the code I handle them, but I cannot tell from the datasheet whether they are independent. top.sv
  2. Hello, I have issues with DDR4 ipcore design in PL part. Also I am using vivado 2019.2 version.I want to redesign and use DDR4 and I want to write and read huge data sets into the DDR4 in vivado as IPCORE but I could not find any resources about how can we create custom ddr4 ip core. Can you helo me about these issues as soon as possible? Thank you. Best Regards.
  3. Hi. I'm using zynq board. I'm a beginner. In my design, I used aurora8b10b IP (with framing mode) . It has AXI_ tdata, tkeep ,tlast,tvalid port. I controlled these signal in my custom logic. What I want to do is reading a frame data from aurora on the PS side. When I see the axi stream fifo, I have similar ports. Can I use this? Or should we use DMA? Please tell me the proper way. thanks
  4. Dear All, "I'm working with Vivado 2018.3 and a Zybo Z7020 board" I write here because I have a very strange problem in a project that I have been developing in the past months. Namely, I've been writing a verilog code to run on a Z7020 board. This code takes user input as parameters (that are hence hard-coded) and everything works fine with this project (no errors or not understandable warnings...) Now, my job is to make sure that these so-colled parameters can be changed through a serial connection from a laptop. Hence, I've packaged my module in an IP and connected it to the PS, programmed the SDK and here is the problem : Many things work but some don't. At the beginning, I thought that the SDK used a different convention to represent signed integers (two complement, only first bit changed...) and have thereby checked that the parameters sent by the SDK where equal to hard coded values in the PL... and they are! Every single bit.. I'm now out of option to understand my problem... Has anyone had similar issues in the passt? Does anyone have a clue for me? Thank you a lot, P.S. : Please do not hesitate to write a comment if you need any further infos.
  5. Dear all, I'm using Vivado 2018.3 and a Zybo Z7010 board. I have finally finished my project (I actually owe this forum much), and I am now trying to use the board without having to open nor Vivado neither the SDK. Basically, I know that I can program the QSPI flash memory of the board so that the program can run without having to upload it. How this works is still unclear, is switching from JTAG to QSPI enough or should I do something on Vivado? However, I am also using the Zynq processor which runs an application that I start from the SDK. Can I avoid opening the SDK? The better thing would be if I could programm the FPGA through Matlab but I don't know if this is possible. Could you point me to some tutorials or the matlab functions (if they exist...). Thank you very much, NotMyCupOfTea
  6. Hi, Problem : I am new to FPGA and I would need to understand how to read an Analog input through the XADC to analyze it on the board and then be able to accordingly output a trigger for other machines. One simple thing that I would try to do for the time being is to read in the analog signal and wire it to a led so that I could effectively see the code is working. How do I do that ? Finally, one extra constraint is that I have to limit as much as possible the use of the Zynq processor (I'm not really sure this is achievable, please excuse my lack of knowledge). Product : I use the Zybo Z7 board XC7Z010-1CLG400C and Vivado Design Suite 18.3 What I have tried : I think the tutorial I've seen that best suits be needs is this one : https://cdn.instructables.com/ORIG/FRT/SYN1/IWMMH04D/FRTSYN1IWMMH04D.pdf Everything is alright until it comes to copy the instantiation template into the wrapper. I'm not really sure of how this works. After that, it is said there that the Digital input I'm interested in is named "daddr_in" ==> how should I extract it then to - let's say - connect it to a led ? Please find the Constraint file and project in the attached files and let me know if you need more. I have also made other attempts through this : http://realisenow.sdu.dk/using-the-xadc-on-the-zybo-board/ Hence a question on the fly : when I open the SDK and enter a code in C, then I'm starting to ork on the PS isn't it ? Finally, I have also tried the XADC demo project on the digilent website but couldn't sort out how to adapt it to my needs. Thank you in advance for your healp, ! Zybo-Z7-Master.xdc design_1_wrapper.v xadc_wiz_0.v
  7. Hi, I am working on a project where i use four UART for an application, all four uart lines sends and receives approx. 20 bytes of characters and expects 20 bytes o character in every 16 milliseconds. And the data transfer will be continuous. NOTE : All four UARTs, are on PL side and controlled by PS of my zynq SoC.. NODE B : Zybo NODE A : Subsystem The UART communication is between NODE A and NODE B. NODE A sends data to NODE B, in turn NODE B should receive the data and reply with an acknowledgement. In this case NODE B is my Zybo Node A is another subsystem. So the data transmission is initiated by NODE A and the control is with NODE A. NODE A will Enable the data transmission for all four UARTs. Now the problem which i am facing is, when NODE A enables the transmission for any two of the UART lines the data transmission is smooth, the problem arises only when i enable the other two. Which means the zybo is not capable of attending to those interrupts which is simultaneously coming from NODE A through four UART lines. My data contains Start byte and Stop byte, Both Start and stop byte are same character. I will attach a my Interrupt handler for reference. **************NOTE************** UART IP on PL side : UART16550 Type of UART : Interrupt driven. Software used : Vivado 2018.3 and SDK Bare metal software. UART interrupt priority : equal priority for all four UARTs. ********************************** I am not very sure about how to use four UARTs efficiently with my Zybo . Please help me with the problem, any inputs from your side will be appreciated. The following is my UART interrupt handler. *************************************************************************** static void RW1RecvHandler(void *CallBackRef, unsigned int EventData) { int i, ch, RecvCount, index; RecvCount = EventData; // repeat this loop for all chars received, i.e., for all ReceivedCount i = 0; while (i < RecvCount) { ch = RW1_RecieveBuffer[i++]; // get the received char from the buffer if(RW1_Start_byte_flag == 1) { // Stop Byte Check for RW1 if (ch == 0xc0) { // Ignore one of the two successive start byte characters if (RW1_ReceivedCount > 1) { RW1_Start_byte_flag = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; RW1_Frame_complete_flag = 1; } } else { if ((index = RW1_ReceivedCount) < TEST_BUFFER_SIZE) { RW1_Buffer[index] = ch; RW1_ReceivedCount++; } else RW1_Start_byte_flag = 0; } } // Start Byte Check for RW1 else if (ch == 0xc0) { RW1_Start_byte_flag = 1; RW1_ReceivedCount = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; // Note the cpu time when first character is received XTime_GetTime(&t_start_RW1); RW1_Frame_complete_flag = 0; } } if(RW1_Frame_complete_flag == 0) { // set up the buffer for next char in interrupt mode XUartNs550_Recv(&RW1, RW1_RecieveBuffer, 1); } } Thanks & Regards Ajeeth Kumar