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Found 6 results

  1. I’m trying to debug a program Factorial.c on the Nexys A7 50T FPGA board using PlatformIO. I have procured its bitstream file from the GitHub repository. Shown below is the platformio.ini code: [env:swervolf_nexys] platform = chipsalliance board = swervolf_nexys framework = wd-riscv-sdk monitor_speed = 115200 board_build.bitstream_file = D:\STUDIES\NexysFiles\Nexys-A7-50T-OOB-2018.2-1\vivado_proj\Nexys-A7-50T-OOB.runs\impl_1\nexys50t.bit Shown below is the program code: #if defined(D_NEXYS_A7) #include <bsp_printf.h> #include <bsp_mem_map.h> #include <bsp_version.h> #else PRE_COMPILED_MSG("no platform was defined") #endif #include <psp_api.h> #define N 7 int main(void) { int fact = 1; int temp = N; while(temp > 0){ fact *= temp; temp -= 1; } uartInit(); // Initialize UART printfNexys("Factorial of %d: %d ", N, fact); } Using PlatformIO, the bitstream is uploaded successfully on the board: After clicking on “Run Debug”, the compilation is also done successfully: But the debug console fails with the following errors: My current driver used is: I have installed it using Zadig and have also tried reinstalling the driver but the same issue persists. Please help me resolve this issue.
  2. Hi, I am wondering which wall power supply to choose for the Nexys A7 100T board since the power supplies available at the digilent store do not refer to it in their descriptions. A recommendation would be very helpful for me. Thank you!
  3. Hi! I'm working with porting an FPGA design with a soft core CPU to the Nexys A7 100T board. The CPU's SW is polling a PS/2 keyboard each 16ms by releasing the PS2_CLK (changing the pin 0->Z, i.e. inhibit release) during ~100µs. This works fine on the earlier design that uses a real PS/2 keyboard, but it fails with using the USB -> PS/2 emulation on the Nexys A7 board. A deeper investigation shows that real PS/2 keyboard responses with lowering the PS2_CLK signal 25-35µs after the CPU has change the PS2_CLK pin 0->Z, while the Nexys PS/2 emulation seems to require up to 420µs before it responses. What is the specified max response time after inhibit for the PS/2 emulation implementation? Would it be possible to have a FW update that lowers this time? I also noted that the link to the Release page under "Demo Setup" on points to the wrong URL (I assume that the correct URL should be and the demo shows the keyboard code on the 7-segment display, not via the serial port. Best regards, Per-Olof
  4. Greetings, Just bought the Nexys A7-100T was using Nexys 2 up until now. Currently using ISE 14.7 looking for the User Constraints file for this board in the resource page nowhere to be found. There is in the examples a .xcf file which does not help me at all. Tried to type in a simple .ucf file no luck there example below. Tried to use the .xcf file that does not work. Renamed the .xcf file to .ucf file that does not work. NexysA7.ucf Frustrated with new board cannot even get it to make a simple Adder. I receive the following error when generating the bit file. I have included my source a simple Full_Adder instantiated from the system entity in system.vhdl file. Started : "Generate Programming File". Running bitgen... Command Line: bitgen -intstyle ise -f System.ut System.ncd ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you may apply the following bitgen switch: -g UnconstrainedPins:Allow INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most commonly, bitgen has determined and will use a specific value instead of the generic command-line value of "Auto". Alternately, this message appears if the same option is specified multiple times on the command-line. In this case, the option listed last will be used. ERROR:Bitgen:157 - Bitgen will terminate because of the above errors. Process "Generate Programming File" failed System.vhd Multiplier.vhd
  5. Hi, I am trying to establish a lowpass filter to Audio Demo code of Nexys A7 board. I have implemented a filter however i hear just a noise. If you share your time, i will be happy. I have added the project which was generated by Vivado 2018.2. Vivado Project Best regards.
  6. Hello, I am using the Nexys A7-100T board.And I'm able to successfully read external input voltages on XADC Demo provided in the " ". I want to measure external input voltage(taken from measurement system) and show the parameter on PC. Now I try to modify the XADC Demo program,but I am still a beginner so I can't succeed. Please let me know how to do for making program. thanks marimo