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Found 2 results

  1. Hello, I'm using "Mipi-csi2 rx subsys" on KC705 & 0V5640 with FMC Digilent adapter. I obtain data from d-phy (fig1) but I can't obtain TVALID signal from AXIS output. Mipi-csi2 rx subsys is set to decode YUV422 10 bit signal, on 2 Lanes with LaneRate to 280Mbps. I modify the Xilinx cfg_init tab from 0V5640.h and set register: {0x3034 || 0x1A} 10bit {0x300e || 0x45 } MIPI enable || Two lane mode {0x4800 || 0x14} [5]=0 Clock free running, [4]=1 Send line short packet, [3]=0 Use lane1 as default, [2]=1 MIPI bus LP11 when no packet; Default=0x04 {0x4300 || 0x30} Format Control (YUV) Edit: I read from ISR=0x00022882: bit2-ErrFrameSync VC0=1 | bit7-ErrFrameSync VC3=1 | bit11-ECC 2-bit error | bit13-SoT error detected bit17-StopState Q0 How to set 0V5640 register 0to obtain valid frame with YUV10bit config? Q1 Which condition are needed to generate tvalid on axis output? Q2 Is there register to set to generate axis transaction from "Mipi-csi2 rx subsys"? Regards.
  2. I'm trying to communicate with a Digilent JTAG-SMT1 on an older Xilinx KC705 from a Raspberry Pi 3 and I've successfully been able to communicate with it via cmd line. Now I want to convert the 2-wire demo to a 4-wire demo since the SMT1 can only support 4-Wire JTAG. The only problem is that I've had a hard time understanding what the difference between the two is. I just need a push in the right direction since I've gone through the API trying to understand it and I've made very little progress. Thank you for your time.