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Found 3 results

  1. Hi all, I'm looking for an IBIS model or some sort of simulation model for the JTAG-SMT2. Please let me know if there is one available or something that I can use/reference for my SI simulations. Thanks!
  2. Hi, I'm working on a project based on a Xilinx Ultrascale+. The final board will contain, for JTAG interface, a SMT2-NC device with a USB type-C receptacle. This board should work as "device", and so as Upstream Facing Port (UFP). At the moment, I know how to treat the CC lines (via 5.1 kOhm pull-down resistors) but I still don't understand how to connect (or how to use) the VBUS lines, because the SMT2 is powered from the 3.3V and VREF pins and not VBUS. Can I leave the VBUS lines unconnected or I should follow some specific procedure to connect them? Thanks
  3. We are using a JTAG-SMT2-NC for JTAG access through one of our daughter cards. This has worked in the past using KU115 and VU5P FPGAs paired with a Zynq. However now the VU9P the JTAG chain is unstable in Adept and Vivado hardware manager where most of the time it will not correctly scan the chain and give device IDs that do not match with devices in the chain. Is there an incompatibility with the JTAG-SMT2-NC and the VU9P FPGAs? Thanks, David
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