Search the Community

Showing results for tags 'hello world'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Test and Measurement
    • Measurement Computing (MCC)
    • Add-on Boards
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions
    • Archived

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 4 results

  1. Just got myself a zedboard. says "copyright 2020" on the silkscreen so its fairly new. I'm stepping through the instructions here: https://reference.digilentinc.com/programmable-logic/guides/getting-started-with-ipi I'm using Vivado v2020.1 (64-bit), and Xilinx Vitis IDE v2020.1.0 (64-bit) because that seems to be the recommended version of tools for that tutorial. I tried a later version and a lot of the screenshots were completely different. When I get into vitis, I select the system project in the Assistant pane, and click the Build button (hammer). I get the following under the "Problems" tab: Description Resource Path Location Type fatal error: xgpio.h: No such file or directory main.c /project_1_app/src line 3 C/C++ Problem make: *** [makefile:38: package] Error 1 Debug /project_1_app_system C/C++ Problem When I look at the Vitis.log tab, I see the following, withi the zed.xsa error at the bottom: 12:45:48 DEBUG : Registering SDKStatusHandler to handle trace exceptions. 12:45:48 DEBUG : Registered the core plugin as the backup plugin for storing repository paths. 12:45:48 INFO : Launching XSCT server: xsct.bat -n -interactive D:\workspace\temp_xsdb_launch_script.tcl 12:45:48 INFO : XSCT server has started successfully. 12:45:48 INFO : plnx-install-location is set to '' 12:45:48 INFO : Successfully done setting XSCT server connection channel 12:45:48 INFO : Successfully done setting workspace for the tool. 12:45:48 INFO : Platform repository initialization has completed. 12:45:48 INFO : Registering command handlers for Vitis TCF services 12:45:48 INFO : Successfully done query RDI_DATADIR 12:45:57 INFO : Checking for BSP changes to sync application flags for project 'project_1_app'... 12:46:03 ERROR : (XSDB Server)ERROR: [Hsi 55-1571] The design file D:/workspace/project_1_wrapper/export/project_1_wrapper/hw/zed.xsa is already opened at which point, the Vitis.log stops there. I've seen the "fatal error: xgpio.h: No such file or directory" on other posts this forum and elsewhere, but I have not seen a definitive answer to how to fix it. The only specific "try this" thing I've seen is try refreshing and try going back to vivado and rerun synthesis, implementation, and bitstream. Neither fixed the problem for me. I followed these instructions to download board files: https://reference.digilentinc.com/programmable-logic/guides/installation I copied the "new/board files" because instructions say that is for versions later than 2014.4 And when I google for "zed.xsa is already opened", I don't find it anywhere. any help would be appreciated
  2. Hi, Where can I find a tutorial to run 'Hello World' with Vivado 2020.1 and Vitis to run on Nexys A7-100T ? I've searched everywhere, including this forum, and couldn't find a tutorial. I tried a tutorial on YouTube for the Artix 7, and I'm unable to generate a bitstream. I get this critical warning: [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port reset_0 can not be placed on PACKAGE_PIN C12 because the PACKAGE_PIN is occupied by port reset. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["c:/Users/curti/XilinxProjectsCurtis/HelloWorld_hw/HelloWorld_hw.srcs/sources_1/bd/HelloWorld_design/ip/HelloWorld_design_rst_clk_wiz_1_100M_0/HelloWorld_design_rst_clk_wiz_1_100M_0_board.xdc":3] And I get these errors: [DRC NSTD-1] Unspecified I/O Standard: 2 out of 8 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: diff_clock_rtl_clk_n, and diff_clock_rtl_clk_p. [DRC UCIO-1] Unconstrained Logical Port: 3 out of 8 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: reset_0, diff_clock_rtl_clk_n, and diff_clock_rtl_clk_p. I'm a new user of Vitis, and relatively new to Vivado. Can anyone offer suggestions on how to correct the errors? Or, better yet, where can I find a tutorial that works to run 'Hello World' with Vivado 2020.1 and Vitis to run on Nexys A7-100T ? My thanks in advance for any suggestions, Curtis
  3. Hello I tried HelloWorld example in Vitis and Vivado 2019.2 and this worked well until programming FPGA. Because I have only one USB cable to connect into zedboard PROG port or UART port, I ran a HelloWorld program with "RunAs -> Launch on Hardware(System Project Debug)" with connecting cable to PROG port and reconnected to UART port to receive outputs from zedboard. However, I got weird results(e.g. there is no outputs or there is outputs but garbled). After that, I borrowed a cable from my friend and also connected it to zedboard, and I rerun program and got appropriate outputs. My question is whether I must have two cables to connect two ports when programming FPGA and run program by jtag. If not, please tell me how to do that.
  4. I'm using Vivado 2019 and a Zedboard, trying to implement "HelloWorld" in PS and output "Hello World" at PC terminal.but it doesn't work. usb-uart and usb-jtag is connected with PC (Win10) i'm using mio-46,47 to uart0 please help me... my step: 1. vivado open block design > HDL wrapper 2. run implementation 3.Export Hardware 4. launch SDK > new application project 5. open putty for monitor (COM4, speed is 115200) 6. SDK run configuration and the setting as following > Run 7. run result as following 8. the com port terminal is nothing... please let me know where i do the wrong step.. thank you very much.!!!