Jump to content

Search the Community

Showing results for tags 'ddr memory'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Test and Measurement
    • Measurement Computing (MCC)
    • Add-on Boards
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions
    • Archived

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 2 results

  1. Hi, I impelemnted a design composed of a softcore processor (RISC-V based), on a Nexys 4 DDR (Nexys A7) board. The software is stored in the DDR2 Memory. The software accesses the DDR2 memory through a controller interface. Now, I'd like to add an Audio IP that can fetch some audio samples, stored in a specific location (by the processor) in the DDR2 memory, and feed them to the audio output. However, since the interface is taken by the processor, is there a way to use that interface by the audio driver too? I read about something called the Ping Pong PHY, but apparently it is only supported in DDR3 and DDR4. Is there any equivalent way to do that?
  2. Hi guys, happy new year!! I'm currently trying to write and read data from my DDR3 SDRAM block. Instead of using any IP core, I want to write and read data diractly using Verilog in Vivado. But unforunitely, I can't find the XDC configition in XDC file of my board. so I'm stucking at how t `timescale 1ns / 1ps //ram.v module ram( input clk_i, input rst_i, input wr_en_i, input rd_en_i, input [7:0] addr_i, inout [31:0] data_io ); reg [31:0] bram[255:0]; integer i; reg [31:0] data; //add implementation code here always @(posedge clk_i or posedge rst_i) begin if (rst_i) begin for(i=0;i<=255;i=i+1) //reset bram[i] <= 32'b0; end else if (wr_en_i) begin bram[addr_i] <= data_io; end else if (rd_en_i) begin data <= bram[addr_i]; end else begin data <= 32'bz; end end assign data_io = rd_en_i? data : 32'bz; endmodule Mater xdc file for arty-35.txto realize my XDC. The attachment is DDR3 CIRCUIT, XDC file and My verilog code
×
×
  • Create New...