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Found 7 results

  1. I am trying to figure out how to write to the RESET_AWG port here in SDK in hopes I can reset the DAC after every send of Data sent to help with creating a noise generator. Currently the DAC is outputting the same data consistently for upwards of a few milliseconds before it eventually is updating to the new value I send it. I am hoping by forcing a reset, this won't occur and more and the data buffer sent will only output once and then send a new array of data out/
  2. I am looking for the DAC 1411 datasheet so that I may find the SFDR (Spurious Free Dynamic Range) specifications.
  3. Hello everyone, I am looking for an ADC and a DAC of at least 2 MSPs and a resolution greater than or equal to 12 bits. I do not want to use ADC or DAC with an FMC type interface (I do not have enough free pins on my FPGA card). A serial type interface (SPI) would be nice. Are there PMODs that have these characteristics? If not, can you recommend an ADC / DAC with these characteristics (> 2 MSPs and> 12 bit resolutions)? I have to process signals of frequency <= 10 kHz and send them to a DAC with a resolution of at least 12 bits and an acquisition speed of at least 2 MSPs. Thank you! Regards H
  4. Div_01

    Nexys2 FPGA board

    Hi, I am a newbie to FPGA. Does the Xilinx Spartan 3E Nexys2 FPGA board contain internal ADC and DAC? If yes, which are the ports for it? Thanks & Regards, Divya
  5. Hey Digilent, I've successfully run the low_level_zmod_adc_dac demo on my board with a ADC and DAC ZMOD. I next decided to run the zmod_dac demo using both petalinux and baremetal. I was able to program the FPGA and also run the code, however every time it attempts to allocate a buffer to transfer the waveform via AXI DMA malloc is returning a 0/NULL value for the buffer address. If I am correct this means that malloc is unable to obtain memory. I'm running this demo as is directly from your git repo. The error that occurs due to this 0 buffer address varies, for petalinux it causes a memory violation error when it tries to copy the waveform to the buffer. For bare metal it copies fine, but then the AXI DMA copy never completes presumably due to the bad 0 address. Do you have any tips for me on how to get this demo running? If there is any additional information I can provide just let me know. I did find it curious that fnAllocBuffer takes an "addr" corresponding to the dmaAddr on the zmod but then doesn't use it for anything, could that be related? Thanks! void* fnAllocBuffer(uintptr_t addr, size_t size) { uint32_t *buf = (uint32_t *)malloc(size); return buf; }
  6. Hello everybody, I want to implement a dac example into my fpga board (MYD-C7Z015). My input will be 32 bit. First 4 bits are command bit which are C3=0, C2=0, C1=1, C0=1. Next 4 bits are Don't Care Bits. After Don't Care Bits, 12 Bits will be nothing(space). Then the rest 16 bits will be my data.In other words, I try to implement LTC-2601 to 32 bit input. Now I have an IP with one output port. This Slave Ip has 4 registers. Also I use Zynq-7000 Processing System IP. In each rising edge of Zynq 7000 Processing System IP's clock I look at one bit and assign that bit to my slave register (in this example slv_reg0). Since my oscilloscope can measure up to 350 Mhz, I have to decrease the frequency of clock. That's why I just do this process in 20 rising edge of clock. In SDK part of my project, I just send some data to my slave register with Xil_Out32 function. However, after all this process the result is considerably different than I expected. My oscilloscope shows the only impulses. Also this part does not work properly. I expected a really nice square wave. But in the implementation it has some fluctuation in the wave. I leave my VHDL code below. Thank you. port( -- Users to add ports here output : out std_logic := '0'; -- User ports ends ); -- Add user logic here -- S_AXI_ACLK is the clock from Zynq-7000 Processing System IP. process(S_AXI_ACLK) variable index : integer := 0; variable counter: integer := 0; begin if rising_edge(S_AXI_ACLK) then case index is -- 4 Command Bits start when 0 => output <= '0'; when 1 => output <= '0'; when 2 => output <= '1'; when 3 => output <= '1'; -- 4 Command Bits end -- 4 Don't Care Bits start when 4 => output <= '0'; when 5 => output <= '0'; when 6 => output <= '0'; when 7 => output <= '0'; -- 4 Don't Care Bits end -- 16 Data Bits start when 8 => output <= slv_reg0(16); when 9 => output <= slv_reg0(17); when 10 => output <= slv_reg0(18); when 11 => output <= slv_reg0(19); when 12 => output <= slv_reg0(20); when 13 => output <= slv_reg0(21); when 14 => output <= slv_reg0(22); when 15 => output <= slv_reg0(23); when 16 => output <= slv_reg0(24); when 17 => output <= slv_reg0(25); when 18 => output <= slv_reg0(26); when 19 => output <= slv_reg0(27); when 20 => output <= slv_reg0(28); when 21 => output <= slv_reg0(29); when 22 => output <= slv_reg0(30); when 23 => output <= slv_reg0(31); -- Data Bits end when others => end case; if counter = 0 then index := (index + 1) mod 24; end if; counter:= ( counter +1) mod 20; end if; end process; -- User logic ends Note: This vhdl code is from my axi peripheral ip. The rest of the ports, entity, logic and etc is created by the ip itself. So I did not put them here.
  7. Hi everyone, After having succesfully managed to use de XADC of the Zybo Z7010 board as explained in this post, I am now trying to use a DAC Pmod (reference and documentation here). After having checked the documentation, I have tried to write the SPI connection to the DAC (please find the verilog file and simulation in the attached files). Note, that I have decided to set the l_dac signal to 0 to enable continuous output to an oscilloscope. The simulation seems to run well to me and to be in accordance with the documentation, however, the result is not satisfactory. Indeed, the signal I want to output is on 16-bits and the command "output = 16'b1111111111111111", which should give the max value does not reach it. Besides, when I ask to "output = 16'b1000000000000000", which should give half of the max signal, the output is almost zero. Finally, please find in the attached files the image I get on an oscilloscope when I input a sine signal with 0.5V offset and 1Vpp. Does aybody see what I am missing ? Don't hesitate to ask more details if needed. Thank you in advance, DAC_wiz_0.v DAC_wiz_0.sim