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Found 3 results

  1. Hi everybody! I got a new Digilent Cmod S7 Board (Spartan 7) and after some led blinking I'm trying to program a simple High Speed SPI transmitter (just sending "01010101" for the first attempt). For this I used the Vivado Clock-Wizzard to generate both a 300MHz clock (for internal signals) and the 150MHz SPI Clock itself out of my 12 MHz onboard oscillator using the "MMCM" and basically the standard settings. Now, my problem is, when I connect my Logic Analyzer (Digilent Digital Discovery) to the 150MHz SPI Serial Clock Pin (Pin 3, which is Package Pin M3) the Duty Cycle changes around and the signal looks really bad. Just for comparison I also generated a 100MHz-Clock which looks much better (but also not perfect over time). I also output the 12MHz oscillator to a pin, which looks good. I did already read this forum question and so I tried to "cascade to stages" meaning I created two Clock Wizzards, the first one creating a 50MHz clock feeding the next one which creates my 150MHz clock. => Signal still looks bad. I also tried to change some settings in the clock wizzard with no success. Is this a problem of input jitter? Or is the output stage of my device to slow (I think not)? Can anybody explain the root cause of this problem and if there is a simple workaround? Thanks and Best regards! ------------------------------------------------------------------ ------------------------------------------------------------------
  2. Hello, I have an aoutomatic test equipment(ATE) that contains a BSCAN device. In order to test that device I have picked a Cmod C2:Breadboardable CoolRunner-II CPLD Module and put it into my selftest adapter (ITA). The only thing I want to do is running a connection test to Cmod C2. But I need the netlist of Cmod C2 otherwise I cannot create a BSCAN project(using XJTAG). Can you please provide the netlist? I can submit my company information and anythişng else that required. Thanks in advance. Furkan.
  3. How do I implement an external differential clock in VHDL for the CMOD S7? Vivado keeps on telling me to inset this flag in my constraint file: set_property CLOCK_DEDICATED_ROUTE FALSE However, I care about timing because it's an external clock signal. I'm using a clock dedicated route(Pmod pin are 2×6) as seen in this schematic.