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Found 5 results

  1. Hi there! I'm an electrical engineering student and my group has been thrown in cold water: We have to do an SPI Project where we connect a PMOD-Mic3 to our Basys3 Board and measure the frequencies of sounds by giving the Mic signal out to the onboard LEDs. A lot of LEDs have to light up when the frequency is high (over 500 Hz) and less when the frequency gets lower. [We have to create a Vivado VHDL Project.] We have huge problems understanding the core of the exercise. So far, after hours of research, we were not succesful with anything but especially: Establishing SPI-Communication (Master-Slave) Creating working shift-registers Our question is: has anyone done anything like that and can provide us with tipps/tricks or even a working examplary code? We value copyright and would never copy your work, we just need an idea as we have never dealt with FPGAs, VHDL or SPI before. We would appreciate every answer, thank you all a lot in advance! Your ElectricalEngStudent :)
  2. Hi I'm trying to use the RGB to DVI ip to acquire video, and I'm getting placement errors. if I unpackage IP, I, can't find any "conflictive" setting related to placement, in the sense that there isn't any physical pin reference at all and ISERDES instances look good. I'm providing the 200mhz ref clock to properly drive input delays and I'm not using any external constraint file. How can I fix or check that there isn't anything wrong? The board (and related configuration) being used is a nexys Video, and compiling with Vivado 2021.1. The rest of the design has a microblaze, some buttons and leds and the DDR3 memory controller. I'm using the latest IP version from the Digilent IP Repo. Thanks
  3. I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code.... whichever way possible.
  4. Hello Digilent Forum! I have been able to run the Cmod A7 Out of Box Demo and export it to an SDK/Vitis project, then modify memorytest.c to write and read new data to and from the SRAM. What a great demo for getting started with the Cmod A7! However, I would like to configure the external memory controller (AXI EMC) block to use its individual ports -- without using the Cmod A7 board file and the "cellular_ram" port from the EMC_INTF pin of the EMC block. I created a new project that uses the xc7a35tcpg236-1 FPGA (not the board file), edited the constraints XDC file, and pinned out the EMC block to match the specs of the onboard ISSI IS61WV5128 SRAM; but it fails to generate a bitstream file successfully. I have also tried to setup tristate buffers (IOBUF) at the top level similar to the demo project's user_35t_wrapper.v file does, but no luck. Configuring the EMC signals (mem_dq_i, mem_dq_o, mem_dq_t, mem_dq_io) for a tristate buffer to interface with the SRAM's data lines seems to be the most confusing part. An image of what I "think" the EMC block should look like is attached. Any help interfacing the EMC block and SRAM correctly (without the board file) would be greatly appreciated. Thanks! Ian
  5. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about adding an RTL module, which seemed more appropriate because I want to be able to modify quickly as I go, and in the same project. Based on what I've read, I was thinking to make an RTL module with a Slave AXI-lite interface (not sure how to do the registers though?), then use a master AXI-stream to pump the results to a Xilinx DMA IP block. I've been passing Synthesis but getting different Implementation errors ("failed to stitch checkpoint", "*.vhd is a black box") doing trial and error with this. All I've done in terms of the code is try to define the entity port to have those two interfaces, either copying from other IPs or using the Language Template (for AXI stream). Is there a good example in VHDL of a barebones AXI peripheral like this, that will pass Implementation? Once that works, I can get into adding those registers and the processing logic. Thank you!
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