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Found 12 results

  1. Normally I would have had a question for the forum now. However, shortly before sending the question, I found the cause of the problem myself. As it turned out, it is not a problem but only a lack of information about the Vivado development environment. Therefore, here is my question and the direct answer to it. (so that others don't waste their time) The question would have been: I have written a small Verilog description which only flashes one LED. It can be programmed into the board with the USB cable and it works. Then I tried to program this Verilog description with a "bin file" so that after a restart (power-on) this corresponding function is executed immediately. Unfortunately, the programming of the flash memory has overwritten the old data, but the test function is not started after a power-on. During programming, it was reported that everything had worked. (Deleting the memory and reprogramming) It is not clear to me why the Verilog description only works when programming with a "bit stream". I use the BASYS board with the Vivado "Version 2020.2". Thank you in advance for any information on the cause of the problem or a description of the solution. The answer is: If you restart the board (power-on) then the desired function is loaded from the memory and immediately executed in the FPGA. But only if the Vivado development environment is not started on the connected computer. If it is not started, the board can remain connected to the computer with the USB cable for the board's power supply. Then, after switching on the board with the power switch, everything starts without errors. Switching on when Vivado is running prevents execution from the flash memory. So no answer is required ! However, as information, this contribution should remain in the forum.
  2. Is this insane? Can I wire a PMOD port, specifically pins JA10 and JA4 as a differential receive port for a UDP project? The brilliant guy who wrote this on fpga4fun.com built a circuit to generate a common mode input. If I attempt to wire RD+ and RD- directly to a differential pin pair in the PMOD port, am I wasting my time? Damaging my Basys3? I'm thinking about starting by hooking it up with a project that is designed just to run an ILA and see what happens. I am expecting these receive signals to be plus and minus 2.5v. I would like to wire those pins to an IBUFDS. Please talk me out of this if I'm about to do something very stupid. I fear I am about to embark on one of those "hold my beer" and "hey watch this" moments.
  3. Hi Guys I am trying to communicate with my Basys 3 board using USB-UART Bridge (Serial Port) and TeraTerm software but with no success. the weird part is that my device is recognizable by the Hardware Manager of Vivado and i can send the bitstream file successufly to program my FPGA but it is not showing up in the Hardware Manager of Win7 as seen in the attached cut out, so i dont know which COM Port is connetected to (if that's the case ) to be able to communicate with my board serially. I tried installing FTDI FT2232HQ USB-UART bridge driver from www.ftdichip.com but didn't solve my problem. I will be more than grateful if you could help me sort this problem out Regards,
  4. Hello I am creating a verilog module on the basys 3 board to interface with the Pmod DA3. I have tried running the module with the DA3 connected and wasn't getting any voltage reading. I have my sclk speed at 25Mhz. Below is my current code and screenshots of my test bench and the pmod outputs on an oscilloscope. Any help is appreciated. `timescale 1ns / 1ps module sclk( input clock, input reset, output sclk ); reg[24:0] count = 0; reg sclk = 0; always @ (posedge clock or posedge reset) begin if (reset ==1'b1)begin count <= 0; sclk <= 0; end else begin count <= count + 1; if(count == 1) begin sclk <= ~sclk; count <= 0; end end end endmodule __ `timescale 1ns / 1ps module spi0( input clock, input reset, input send, output sclk0, output reg cs, output reg ldac, output reg din ); reg[15:0] data [3:0]; reg[15:0] count; reg [1:0] sel; sclk sclk_inst ( .clock(clock), .reset(reset), .sclk(sclk0) ); initial begin data[0] = 16'b0101111000010101; data[1] = 16'b1000011111100001; count = 16'd16; cs = 1; sel = 0; end always @ (negedge sclk0 & send == 1)begin if (send == 1)begin if ( count > 0)begin cs = 0; ldac = 0; end if (count == 0)begin cs = 1; ldac = 1; count = 16'd16; end din = data[sel][count-1]; count = count - 1; end end endmodule __ `timescale 1ns / 1ps module spi0_testbench(); reg clock = 0; reg reset = 0; reg send = 0; reg [50:0]counter = 0; reg [16:0] i; wire sclk0; wire cs; wire ldac; wire din; wire[15:0] count; spi0 UUT(clock, reset, send, sclk0, cs, ldac, din); always @ (*)begin #10 if (i >= 127 & i < 129)begin send = 0; end if (i < 127 | i >= 129) begin send = 1; end if (i < 127)begin end end initial begin for (i = 0; i < 1000; i = i + 1)begin clock = ~clock; counter = counter + 1; #1; end end endmodule Green: SCLK Yellow: DIN Blue: CS Pink: LDAC
  5. this is my first attempt to program an FPGA (I use Basys 3), and when I tried to connect to the hw_server after generating the bitstream , I got this error:
  6. Arduino is the SPI Master and therefore provides the clock, SPICLK through a PMOD. How do I receive the clock in a good way on the FPGA? Vivado does not approve of checking rising_edge(SPICLK) so I though I'd put a clock buffer or something in between (not that I know why or what they do but it sounds like a good idea). At some point Vivado told me to add "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SPICLK_IBUF}]" to the constraints file, but I still got warnings and it didn't recommend I proceed. If I have the top level SPICLK connected to an IBUF_IBUFDISABLE with the disable line connected to the slave select (SS) line, I get this warning: [DRC 23-20] Rule violation (CKLD-2) Clock Net has IO Driver, not a Clock Buf, and/or non-Clock loads - Clock net spi_buf is directly driven by an IO rather than a Clock Buffer or may be an IO driving a mix of Clock Buffer and non-Clock loads. This connectivity should be reviewed and corrected as appropriate. Driver(s): IBUF_IBUFDISABLE_inst/O If I have the top level SPICLK connected to an IBUF_IBUFDISABLE and that into a BUFGCE, with the disable line connected to the slave select (SS) line and the inverse of SS into the CE, I get this warning: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. IBUF_IBUFDISABLE_inst (IBUF_IBUFDISABLE.O) is locked to IOB_X0Y25 and BUFGCE_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 Roughly the same warning was issued with just the BUFGCE. I know there are other ways of polling the input clock from the arduino and treating it as normal signal but I want to do it the "proper" way.
  7. I am having layers of problems with the Pmod MicroSD. My ultimate goal is to get through the wifi example on youtube with a Basys 3. Today I am just trying to do the "hello world" demo for the micro SD Pmod. Issues: [Common 17-69] Command failed: BOARD_PART_PIN cannot be assigned to more than one port ["f:/microSD.srcs/sources_1/bd/microSD_bd/ip/microSD_bd_PmodSD_0_0/microSD_bd_PmodSD_0_0_board.xdc":7] I get this error for 4 pins set_property BOARD_PIN {JB7} [get_ports Pmod_out_pin7_t] set_property BOARD_PIN {JB8} [get_ports Pmod_out_pin8_t] set_property BOARD_PIN {JB9} [get_ports Pmod_out_pin9_t] set_property BOARD_PIN {JB10} [get_ports Pmod_out_pin10_t] Vivado does finish making the bitstream. I then push on incase it works anyway. In the SDK I get another error. 12:28:33 **** Incremental Build of configuration Debug for project uSD **** make all 'Building target: uSD.elf' 'Invoking: MicroBlaze g++ linker' mb-g++ -Wl,-T -Wl,../src/lscript.ld -L../../uSD_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "uSD.elf" ./src/main.o -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: uSD.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 159832 bytes collect2.exe: error: ld returned 1 exit status make: *** [uSD.elf] Error 1 12:28:35 Build Finished (took 1s.389ms) Without really knowing what I'm doing, I read the error and think I need to allocate more local memory to the microblaze. "overflowed by 159832 bytes" I then open up my block design and try to customize the microblaze but see no place in change the memory it is allocated. I used the address editor and increase the allocated memory for the dlmb to 128K and then the ilmb to 128K. If I try 256K for each the validation fails. Then after this I get a slightly better SDK error. 13:13:22 **** Auto Build of configuration Debug for project uSD **** make all 'Building file: ../src/main.cc' 'Invoking: MicroBlaze g++ compiler' mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/main.o" -I../../uSD_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.cc" 'Finished building: ../src/main.cc' ' ' 'Building target: uSD.elf' 'Invoking: MicroBlaze g++ linker' mb-g++ -Wl,-T -Wl,../src/lscript.ld -L../../uSD_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "uSD.elf" ./src/main.o -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: uSD.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 61528 bytes collect2.exe: error: ld returned 1 exit status make: *** [uSD.elf] Error 1 13:13:25 Build Finished (took 2s.724ms) My over flow is down to 61528 bytes. I am doing all this by following the IPI tutorial and just adding the PmodSD to it. here and here Thanks FBOARC PS I am using Vivado 2018.2 as that is the version in the tutorial.
  8. Hello I am attempting to follow this but I am confused about section 2.3. It says to place all the application code in DDR. The Basys3 has no external memory but for the SPI flash. From a SPI flash description from an Arty reference, it says but when I read the Xilinx answer record 63605, it says on step 5. Create helloworld application and link to DDR (in the linker script make sure that this application is executing from DDR) Can someone explain to me how to do this all in the SPI flash? Do I need to somehow set that up in my block design in? I do have the QSPI in my block design already but it is not available to me as an option in the linker script window.
  9. Tells me PmodWIFI is packaged with board value arty and to update my basys3 to the arty. I am confused. Well hang on a second. It finished generating a bitstream and I see no critical warnings in the project summary. In fact if I tell vivado to discard user generated messages in the messages window, the project has no indication of critical warnings at all. Still confused but closer to my goal.
  10. Using Windows 10, my Basys 3 Artix-7 FPGA Trainer Board will not power on. Bought a new USB cable from Digilent and the board still did not power on.
  11. Hello, I am a fairly new to using the Basys 3 and a student using it for a project. I am attempting to output 4 separate variables from the Pmod ports on the board using the JA Pmod part. When I run synthesis, implementation, and then bitstream, I get the same error for all but one of my outputs. My error message: [Common 17-69] Command failed: Site cannot be assigned to more than one port ["D:/LogicLab/SignalsProjectMK1/SignalsProjectMK1.srcs/constrs_1/new/BasysOut.xdc":16] Constraint: ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ##Pmod Header JA ##Sch name = JA1 set_property PACKAGE_PIN J1 [get_ports {o1}] set_property IOSTANDARD LVCMOS33 [get_ports {o1}] ##Sch name = JA2 set_property PACKAGE_PIN L2 [get_ports {o2}] set_property IOSTANDARD LVCMOS33 [get_ports {o2}] ##Sch name = JA3 set_property PACKAGE_PIN J2 [get_ports {o3}] set_property IOSTANDARD LVCMOS33 [get_ports {o3}] ##Sch name = JA4 set_property PACKAGE_PIN G2 [get_ports {o4}] set_property IOSTANDARD LVCMOS33 [get_ports {o4}] (o1-o4 are my 4 variables I want to output) Is my constraint file the cause of this error, and if so, how do I go about correcting my mistake? Thank you for the assistance.
  12. Hello, I am trying to interact with my Basys 3 board through the JTAG port on the board but I am not sure what cable to use with it. The cables listed for sale that I've seen, like the JTAG-HS2, say that they are not needed for Digilent FPGA boards. Is there a cable that is intended for use with the FPGA boards? Thanks, Seth