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Found 3 results

  1. Hi, I had tried using the Pmod MTDS to build some simple projects by using the microblaze with Arty A7-35T. I had followed the "Getting Started with Digilent Pmod IPs" tutorial. The bitstream file was successfully generated and exported to the VITIS 2020.1. After I created an application project in the VITIS 2020.1, I copied the main.cc and MyDispDemo1.cc into the src folder as requested after read the README.txt. However, when I started to build the project, it failed. It seem like missing the library files for the MyDispDemo.cc. I had tried many methods, rebuild it, and try to export the bitstream file again to the VITIS 2020.1. However, the problem still exist. So, is there any steps I miss out? Kindly need some helps in order to make the Pmod MTDS works with the microblaze by using the Arty A7-35T. Thank you very much.
  2. Hello everyone! I am trying to program my Arty-7 A35T FPGA using OLIMEX-ARM-USB-TINY-H, can I do this or not? If yes then How?
  3. Hi guys, happy new year!! I'm currently trying to write and read data from my DDR3 SDRAM block. Instead of using any IP core, I want to write and read data diractly using Verilog in Vivado. But unforunitely, I can't find the XDC configition in XDC file of my board. so I'm stucking at how t `timescale 1ns / 1ps //ram.v module ram( input clk_i, input rst_i, input wr_en_i, input rd_en_i, input [7:0] addr_i, inout [31:0] data_io ); reg [31:0] bram[255:0]; integer i; reg [31:0] data; //add implementation code here always @(posedge clk_i or posedge rst_i) begin if (rst_i) begin for(i=0;i<=255;i=i+1) //reset bram[i] <= 32'b0; end else if (wr_en_i) begin bram[addr_i] <= data_io; end else if (rd_en_i) begin data <= bram[addr_i]; end else begin data <= 32'bz; end end assign data_io = rd_en_i? data : 32'bz; endmodule Mater xdc file for arty-35.txto realize my XDC. The attachment is DDR3 CIRCUIT, XDC file and My verilog code
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