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Found 3 results

  1. Hi Everyone! I need help using the following pmodi2s2 module: - https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ I want to use it to sample audio data from microphone only. So, I've added the i2s receiver IP into my block diagram (attached) and run block automation. Following is the documentation of the IP core I used: - https://www.xilinx.com/support/documentation/ip_documentation/i2s/v1_0/pg308-i2s.pdf The following is a reference manual for the above mentioned PMOD module: - https://reference.digilentinc.com/pmod/pmodi2s2/reference-manual I also created an extra clock in PL fabric named FCLK_CLK1 (11.289MHz requested and got 11.290323 MHz). I couldn't find a PMOD core for the said module so I guessed I'll "make-external" and "constraint" the pins on to the PMOD header in a .xdc file. Now, I don't know what to connect where except for the lrclk_out, sclk_out and sdata_0_in which are obvious from their names. Rest of the configuration is auto generated by block automation. I'm particularly confused regarding the clocking and reset configuration. Please help me out on this I'll highly appreciate.
  2. Hello sir We purchased "Arty-Z7-20" a few weeks ago. We are trying to boot a project using the petalinux. We have followed the manual given in the below links. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1144-petalinux-tools-reference-guide.pdf https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1157-petalinux-tools-command-line-guide.pdf But the Arty-Z7-20 board didn't get booted via jtag or SD card. We have also followed steps provided on belowed github, but it won't work.. https://github.com/Digilent/Petalinux-Arty-Z7-20 Output while running boot command shown below, '$ petalinux-boot --jtag --prebuilt 3 --hw_server-url TCP:127.0.0.1:3121' INFO: Sourcing build tools WARNING: Will not program bitstream on the target. If you want to program bitstream, WARNING: please run petalinux-package --prebuilt to put the bitstream to the prebuilt directory, WARNING: or use --fpga --bitstream option to specify a bitstream. INFO: Append dtb - /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/system.dtb and other options to boot zImage INFO: Launching XSDB for file download and boot. INFO: This may take a few minutes, depending on the size of your image. rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device INFO: Downloading ELF file: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/zynq_fsbl.elf to the target. INFO: Downloading ELF file: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/u-boot.elf to the target. INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/system.dtb at 0x00100000 INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/uImage at 0x00200000 INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/rootfs.cpio.gz.u-boot at 0x04000000 INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/boot.scr at 0x03000000 INFO: SOC Silicon version is 3.1.
  3. Hi, Background: I am sending 3 channels of digitized 12-bit (soon to be 16-bit) data over "long" distances (thus I will be sending the data using LVDS). I will also be sending a 40 Mhz clock signal over LVDS so in total, that will be 3 data channels + 1 clock (= 4 channels x 2 wires/channel = 8 wires). The data rate is 600-720 Mbps per channel for 12-bit and up to 960Mbps per channel for 16-bit for the data lines. Question(s): I would like to use the HDMI connector on the Z7-20 board to get the data in. Is that possible? If so, I would appreciate any information as to how to go about doing this. HDMI has a number of LVDS lines (actually TDMS) and I would like to take advantage of the built in hardware to include deserialization of the data and memory storage. TDMS uses 9/10 bit data but I will use 12 bit to 16 bits. Is the data size fixed in hardware or would I be able to configure that? I'm new to FPGAs but can the data get pipelined directly into memory? If so, is there a way to set the bit endianness as it gets stored into memory? If the above is solvable, I would like to know if I can use both HDMI connectors to do this (I will actually have 2 sensors), both the HDMI in and HDMI out. In theory I just need the data lines and access to memory so I wouldn't think that this would be a problem on the HDMI out as well, but I don't know...which is why I'm asking. If the above isn't possible, are there any other options? I can make an adapter board and deserialize the data to CMOS/TTL digital IO and use the PMOD or shield connectors to send the data to the FPGA but this would be 12 bits/channel x 3 channels = 36 bits at 40 Mhz, (48 bits for 16 bit data). That doesn't leave me very many (or any) lines for output but if that is my only option, is 40 Mhz considered high speed? Thanks in advance.